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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 | /* * Copyright 2014 Linaro Ltd * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi" / { model = "ARM RealView PB1176"; compatible = "arm,realview-pb1176"; chosen { }; aliases { serial0 = &pb1176_serial0; serial1 = &pb1176_serial1; serial2 = &pb1176_serial2; serial3 = &pb1176_serial3; serial4 = &fpga_serial; }; memory { /* 128 MiB memory @ 0x0 */ reg = <0x00000000 0x08000000>; }; /* The voltage to the MMC card is hardwired at 3.3V */ vmmc: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; veth: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "veth"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; xtal24mhz: xtal24mhz@24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; timclk: timclk@1M { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; clock-mult = <1>; clocks = <&xtal24mhz>; }; mclk: mclk@24M { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; clock-mult = <1>; clocks = <&xtal24mhz>; }; kmiclk: kmiclk@24M { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; clock-mult = <1>; clocks = <&xtal24mhz>; }; sspclk: sspclk@24M { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; clock-mult = <1>; clocks = <&xtal24mhz>; }; uartclk: uartclk@24M { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; clock-mult = <1>; clocks = <&xtal24mhz>; }; /* FIXME: this actually hangs off the PLL clocks */ pclk: pclk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; flash@30000000 { compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x30000000 0x4000000>; bank-width = <4>; }; fpga_flash@38000000 { compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x38000000 0x800000>; bank-width = <4>; }; /* * The "secure flash" contains things like the boot * monitor so we don't want people to accidentally * screw this up. Mark the device tree node disabled * by default. */ secflash@3c000000 { compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x3c000000 0x4000000>; bank-width = <4>; status = "disabled"; }; /* SMSC 9118 ethernet with PHY and EEPROM */ ethernet@3a000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <0x3a000000 0x10000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; phy-mode = "mii"; reg-io-width = <4>; smsc,irq-active-high; smsc,irq-push-pull; vdd33a-supply = <&veth>; vddvario-supply = <&veth>; }; usb@3b000000 { compatible = "nxp,usb-isp1761"; reg = <0x3b000000 0x20000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; port1-otg; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "arm,realview-pb1176-soc", "simple-bus"; regmap = <&syscon>; ranges; syscon: syscon@10000000 { compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; reg = <0x10000000 0x1000>; led@08.0 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; led@08.1 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x02>; label = "versatile:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; led@08.2 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x04>; label = "versatile:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; led@08.3 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x08>; label = "versatile:3"; default-state = "off"; }; led@08.4 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x10>; label = "versatile:4"; default-state = "off"; }; led@08.5 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x20>; label = "versatile:5"; default-state = "off"; }; led@08.6 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; led@08.7 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x80>; label = "versatile:7"; default-state = "off"; }; oscclk0: osc0@0c { compatible = "arm,syscon-icst307"; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x0C>; clocks = <&xtal24mhz>; }; oscclk1: osc1@10 { compatible = "arm,syscon-icst307"; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x10>; clocks = <&xtal24mhz>; }; oscclk2: osc2@14 { compatible = "arm,syscon-icst307"; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x14>; clocks = <&xtal24mhz>; }; oscclk3: osc3@18 { compatible = "arm,syscon-icst307"; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x18>; clocks = <&xtal24mhz>; }; oscclk4: osc4@1c { compatible = "arm,syscon-icst307"; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x1c>; clocks = <&xtal24mhz>; }; }; /* Primary DevChip GIC synthesized with the CPU */ intc_dc1176: interrupt-controller@10120000 { compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; #interrupt-cells = <3>; #address-cells = <1>; interrupt-controller; reg = <0x10121000 0x1000>, <0x10120000 0x100>; }; L2: l2-cache { compatible = "arm,l220-cache"; reg = <0x10110000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; /* * Override default cache size, sets and * associativity as these may be erroneously set * up by boot loader(s). */ arm,override-auxreg; cache-size = <131072>; // 128kB cache-sets = <512>; cache-line-size = <32>; }; pmu { compatible = "arm,arm1176-pmu"; interrupt-parent = <&intc_dc1176>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; timer01: timer@10104000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10104000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&timclk>, <&timclk>, <&pclk>; clock-names = "timer1", "timer2", "apb_pclk"; }; timer23: timer@10105000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10105000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; arm,sp804-has-irq = <1>; clocks = <&timclk>, <&timclk>, <&pclk>; clock-names = "timer1", "timer2", "apb_pclk"; }; pb1176_rtc: rtc@10108000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x10108000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pclk>; clock-names = "apb_pclk"; }; pb1176_gpio0: gpio@1010a000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x1010a000 0x1000>; gpio-controller; interrupt-parent = <&intc_dc1176>; interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pclk>; clock-names = "apb_pclk"; }; pb1176_ssp: ssp@1010b000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x1010b000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sspclk>, <&pclk>; clock-names = "SSPCLK", "apb_pclk"; }; pb1176_serial0: serial@1010c000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1010c000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; pb1176_serial1: serial@1010d000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1010d000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; pb1176_serial2: serial@1010e000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1010e000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; pb1176_serial3: serial@1010f000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1010f000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; /* Direct-mapped development chip ROM */ pb1176_rom@10200000 { compatible = "direct-mapped"; reg = <0x10200000 0x4000>; bank-width = <1>; }; clcd@10112000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x10112000 0x1000>; interrupt-parent = <&intc_dc1176>; interrupt-names = "combined"; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&oscclk0>, <&pclk>; clock-names = "clcdclk", "apb_pclk"; port { clcd_pads: endpoint { remote-endpoint = <&clcd_panel>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; panel { compatible = "panel-dpi"; port { clcd_panel: endpoint { remote-endpoint = <&clcd_pads>; }; }; /* Standard 640x480 VGA timings */ panel-timing { clock-frequency = <25175000>; hactive = <640>; hback-porch = <48>; hfront-porch = <16>; hsync-len = <96>; vactive = <480>; vback-porch = <33>; vfront-porch = <10>; vsync-len = <2>; }; }; }; }; /* These peripherals are inside the FPGA rather than the DevChip */ fpga { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; i2c0: i2c@10002000 { #address-cells = <1>; #size-cells = <0>; compatible = "arm,versatile-i2c"; reg = <0x10002000 0x1000>; rtc@68 { compatible = "dallas,ds1338"; reg = <0x68>; }; }; fpga_aaci: aaci@10004000 { compatible = "arm,pl041", "arm,primecell"; reg = <0x10004000 0x1000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pclk>; clock-names = "apb_pclk"; }; fpga_mci: mmcsd@10005000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x10005000 0x1000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>; /* Due to frequent FIFO overruns, use just 500 kHz */ max-frequency = <500000>; bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; clocks = <&mclk>, <&pclk>; clock-names = "mclk", "apb_pclk"; vmmc-supply = <&vmmc>; cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; }; fpga_kmi0: kmi@10006000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x10006000 0x1000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&kmiclk>, <&pclk>; clock-names = "KMIREFCLK", "apb_pclk"; }; fpga_kmi1: kmi@10007000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x10007000 0x1000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; clocks = <&kmiclk>, <&pclk>; clock-names = "KMIREFCLK", "apb_pclk"; }; fpga_charlcd: charlcd@10008000 { compatible = "arm,versatile-lcd"; reg = <0x10008000 0x1000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pclk>; clock-names = "apb_pclk"; }; fpga_serial: serial@10009000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x10009000 0x1000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; /* This GIC on the board is cascaded off the DevChip GIC */ intc_fpga1176: interrupt-controller@10040000 { compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; #interrupt-cells = <3>; #address-cells = <1>; interrupt-controller; reg = <0x10041000 0x1000>, <0x10040000 0x100>; interrupt-parent = <&intc_dc1176>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; }; fpga_gpio0: gpio@10014000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x10014000 0x1000>; gpio-controller; interrupt-parent = <&intc_fpga1176>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pclk>; clock-names = "apb_pclk"; }; fpga_gpio1: gpio@10015000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x10015000 0x1000>; gpio-controller; interrupt-parent = <&intc_fpga1176>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pclk>; clock-names = "apb_pclk"; }; fpga_rtc: rtc@10017000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x10017000 0x1000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pclk>; clock-names = "apb_pclk"; }; }; }; |