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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 | /* * trampoline.S: Jump start slave processors on sparc64. * * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) */ #include <asm/head.h> #include <asm/asi.h> #include <asm/lsu.h> #include <asm/dcr.h> #include <asm/dcu.h> #include <asm/pstate.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/spitfire.h> #include <asm/processor.h> #include <asm/thread_info.h> #include <asm/mmu.h> #include <asm/hypervisor.h> #include <asm/cpudata.h> .data .align 8 call_method: .asciz "call-method" .align 8 itlb_load: .asciz "SUNW,itlb-load" .align 8 dtlb_load: .asciz "SUNW,dtlb-load" #define TRAMP_STACK_SIZE 1024 .align 16 tramp_stack: .skip TRAMP_STACK_SIZE .align 8 .globl sparc64_cpu_startup, sparc64_cpu_startup_end sparc64_cpu_startup: BRANCH_IF_SUN4V(g1, niagara_startup) BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup) BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup) ba,pt %xcc, spitfire_startup nop cheetah_plus_startup: /* Preserve OBP chosen DCU and DCR register settings. */ ba,pt %xcc, cheetah_generic_startup nop cheetah_startup: mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 wr %g1, %asr18 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 sllx %g5, 32, %g5 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5 stxa %g5, [%g0] ASI_DCU_CONTROL_REG membar #Sync /* fallthru */ cheetah_generic_startup: mov TSB_EXTENSION_P, %g3 stxa %g0, [%g3] ASI_DMMU stxa %g0, [%g3] ASI_IMMU membar #Sync mov TSB_EXTENSION_S, %g3 stxa %g0, [%g3] ASI_DMMU membar #Sync mov TSB_EXTENSION_N, %g3 stxa %g0, [%g3] ASI_DMMU stxa %g0, [%g3] ASI_IMMU membar #Sync /* fallthru */ niagara_startup: /* Disable STICK_INT interrupts. */ sethi %hi(0x80000000), %g5 sllx %g5, 32, %g5 wr %g5, %asr25 ba,pt %xcc, startup_continue nop spitfire_startup: mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1 stxa %g1, [%g0] ASI_LSU_CONTROL membar #Sync startup_continue: mov %o0, %l0 BRANCH_IF_SUN4V(g1, niagara_lock_tlb) sethi %hi(0x80000000), %g2 sllx %g2, 32, %g2 wr %g2, 0, %tick_cmpr /* Call OBP by hand to lock KERNBASE into i/d tlbs. * We lock 'num_kernel_image_mappings' consequetive entries. */ sethi %hi(prom_entry_lock), %g2 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1 brnz,pn %g1, 1b nop /* Get onto temporary stack which will be in the locked * kernel image. */ sethi %hi(tramp_stack), %g1 or %g1, %lo(tramp_stack), %g1 add %g1, TRAMP_STACK_SIZE, %g1 sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp flushw /* Setup the loop variables: * %l3: VADDR base * %l4: TTE base * %l5: Loop iterator, iterates from 0 to 'num_kernel_image_mappings' * %l6: Number of TTE entries to map * %l7: Highest TTE entry number, we count down */ sethi %hi(KERNBASE), %l3 sethi %hi(kern_locked_tte_data), %l4 ldx [%l4 + %lo(kern_locked_tte_data)], %l4 clr %l5 sethi %hi(num_kernel_image_mappings), %l6 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6 mov 15, %l7 BRANCH_IF_ANY_CHEETAH(g1,g5,2f) mov 63, %l7 2: 3: /* Lock into I-MMU */ sethi %hi(call_method), %g2 or %g2, %lo(call_method), %g2 stx %g2, [%sp + 2047 + 128 + 0x00] mov 5, %g2 stx %g2, [%sp + 2047 + 128 + 0x08] mov 1, %g2 stx %g2, [%sp + 2047 + 128 + 0x10] sethi %hi(itlb_load), %g2 or %g2, %lo(itlb_load), %g2 stx %g2, [%sp + 2047 + 128 + 0x18] sethi %hi(prom_mmu_ihandle_cache), %g2 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2 stx %g2, [%sp + 2047 + 128 + 0x20] /* Each TTE maps 4MB, convert index to offset. */ sllx %l5, 22, %g1 add %l3, %g1, %g2 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR add %l4, %g1, %g2 stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE /* TTE index is highest minus loop index. */ sub %l7, %l5, %g2 stx %g2, [%sp + 2047 + 128 + 0x38] sethi %hi(p1275buf), %g2 or %g2, %lo(p1275buf), %g2 ldx [%g2 + 0x08], %o1 call %o1 add %sp, (2047 + 128), %o0 /* Lock into D-MMU */ sethi %hi(call_method), %g2 or %g2, %lo(call_method), %g2 stx %g2, [%sp + 2047 + 128 + 0x00] mov 5, %g2 stx %g2, [%sp + 2047 + 128 + 0x08] mov 1, %g2 stx %g2, [%sp + 2047 + 128 + 0x10] sethi %hi(dtlb_load), %g2 or %g2, %lo(dtlb_load), %g2 stx %g2, [%sp + 2047 + 128 + 0x18] sethi %hi(prom_mmu_ihandle_cache), %g2 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2 stx %g2, [%sp + 2047 + 128 + 0x20] /* Each TTE maps 4MB, convert index to offset. */ sllx %l5, 22, %g1 add %l3, %g1, %g2 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR add %l4, %g1, %g2 stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE /* TTE index is highest minus loop index. */ sub %l7, %l5, %g2 stx %g2, [%sp + 2047 + 128 + 0x38] sethi %hi(p1275buf), %g2 or %g2, %lo(p1275buf), %g2 ldx [%g2 + 0x08], %o1 call %o1 add %sp, (2047 + 128), %o0 add %l5, 1, %l5 cmp %l5, %l6 bne,pt %xcc, 3b nop sethi %hi(prom_entry_lock), %g2 stb %g0, [%g2 + %lo(prom_entry_lock)] ba,pt %xcc, after_lock_tlb nop niagara_lock_tlb: sethi %hi(KERNBASE), %l3 sethi %hi(kern_locked_tte_data), %l4 ldx [%l4 + %lo(kern_locked_tte_data)], %l4 clr %l5 sethi %hi(num_kernel_image_mappings), %l6 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6 1: mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 sllx %l5, 22, %g2 add %l3, %g2, %o0 clr %o1 add %l4, %g2, %o2 mov HV_MMU_IMMU, %o3 ta HV_FAST_TRAP mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 sllx %l5, 22, %g2 add %l3, %g2, %o0 clr %o1 add %l4, %g2, %o2 mov HV_MMU_DMMU, %o3 ta HV_FAST_TRAP add %l5, 1, %l5 cmp %l5, %l6 bne,pt %xcc, 1b nop after_lock_tlb: wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate wr %g0, 0, %fprs wr %g0, ASI_P, %asi mov PRIMARY_CONTEXT, %g7 661: stxa %g0, [%g7] ASI_DMMU .section .sun4v_1insn_patch, "ax" .word 661b stxa %g0, [%g7] ASI_MMU .previous membar #Sync mov SECONDARY_CONTEXT, %g7 661: stxa %g0, [%g7] ASI_DMMU .section .sun4v_1insn_patch, "ax" .word 661b stxa %g0, [%g7] ASI_MMU .previous membar #Sync /* Everything we do here, until we properly take over the * trap table, must be done with extreme care. We cannot * make any references to %g6 (current thread pointer), * %g4 (current task pointer), or %g5 (base of current cpu's * per-cpu area) until we properly take over the trap table * from the firmware and hypervisor. * * Get onto temporary stack which is in the locked kernel image. */ sethi %hi(tramp_stack), %g1 or %g1, %lo(tramp_stack), %g1 add %g1, TRAMP_STACK_SIZE, %g1 sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp mov 0, %fp /* Put garbage in these registers to trap any access to them. */ set 0xdeadbeef, %g4 set 0xdeadbeef, %g5 set 0xdeadbeef, %g6 call init_irqwork_curcpu nop sethi %hi(tlb_type), %g3 lduw [%g3 + %lo(tlb_type)], %g2 cmp %g2, 3 bne,pt %icc, 1f nop call hard_smp_processor_id nop call sun4v_register_mondo_queues nop 1: call init_cur_cpu_trap ldx [%l0], %o0 /* Start using proper page size encodings in ctx register. */ sethi %hi(sparc64_kern_pri_context), %g3 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 mov PRIMARY_CONTEXT, %g1 661: stxa %g2, [%g1] ASI_DMMU .section .sun4v_1insn_patch, "ax" .word 661b stxa %g2, [%g1] ASI_MMU .previous membar #Sync wrpr %g0, 0, %wstate sethi %hi(prom_entry_lock), %g2 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1 brnz,pn %g1, 1b nop /* As a hack, put &init_thread_union into %g6. * prom_world() loads from here to restore the %asi * register. */ sethi %hi(init_thread_union), %g6 or %g6, %lo(init_thread_union), %g6 sethi %hi(is_sun4v), %o0 lduw [%o0 + %lo(is_sun4v)], %o0 brz,pt %o0, 2f nop TRAP_LOAD_TRAP_BLOCK(%g2, %g3) add %g2, TRAP_PER_CPU_FAULT_INFO, %g2 stxa %g2, [%g0] ASI_SCRATCHPAD /* Compute physical address: * * paddr = kern_base + (mmfsa_vaddr - KERNBASE) */ sethi %hi(KERNBASE), %g3 sub %g2, %g3, %g2 sethi %hi(kern_base), %g3 ldx [%g3 + %lo(kern_base)], %g3 add %g2, %g3, %o1 sethi %hi(sparc64_ttable_tl0), %o0 set prom_set_trap_table_name, %g2 stx %g2, [%sp + 2047 + 128 + 0x00] mov 2, %g2 stx %g2, [%sp + 2047 + 128 + 0x08] mov 0, %g2 stx %g2, [%sp + 2047 + 128 + 0x10] stx %o0, [%sp + 2047 + 128 + 0x18] stx %o1, [%sp + 2047 + 128 + 0x20] sethi %hi(p1275buf), %g2 or %g2, %lo(p1275buf), %g2 ldx [%g2 + 0x08], %o1 call %o1 add %sp, (2047 + 128), %o0 ba,pt %xcc, 3f nop 2: sethi %hi(sparc64_ttable_tl0), %o0 set prom_set_trap_table_name, %g2 stx %g2, [%sp + 2047 + 128 + 0x00] mov 1, %g2 stx %g2, [%sp + 2047 + 128 + 0x08] mov 0, %g2 stx %g2, [%sp + 2047 + 128 + 0x10] stx %o0, [%sp + 2047 + 128 + 0x18] sethi %hi(p1275buf), %g2 or %g2, %lo(p1275buf), %g2 ldx [%g2 + 0x08], %o1 call %o1 add %sp, (2047 + 128), %o0 3: sethi %hi(prom_entry_lock), %g2 stb %g0, [%g2 + %lo(prom_entry_lock)] ldx [%l0], %g6 ldx [%g6 + TI_TASK], %g4 mov 1, %g5 sllx %g5, THREAD_SHIFT, %g5 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 add %g6, %g5, %sp rdpr %pstate, %o1 or %o1, PSTATE_IE, %o1 wrpr %o1, 0, %pstate call smp_callin nop call cpu_panic nop 1: b,a,pt %xcc, 1b .align 8 sparc64_cpu_startup_end: |