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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | /* * Cache maintenance * * Copyright (C) 2001 Deep Blue Solutions Ltd. * Copyright (C) 2012 ARM Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/errno.h> #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> #include <asm/cpufeature.h> #include <asm/alternative.h> #include "proc-macros.S" /* * flush_icache_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, * and will be executed. * * - start - virtual start address of region * - end - virtual end address of region */ ENTRY(flush_icache_range) /* FALLTHROUGH */ /* * __flush_cache_user_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, * and will be executed. * * - start - virtual start address of region * - end - virtual end address of region */ ENTRY(__flush_cache_user_range) dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 1: USER(9f, dc cvau, x4 ) // clean D line to PoU add x4, x4, x2 cmp x4, x1 b.lo 1b dsb ish icache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 1: USER(9f, ic ivau, x4 ) // invalidate I line PoU add x4, x4, x2 cmp x4, x1 b.lo 1b dsb ish isb mov x0, #0 ret 9: mov x0, #-EFAULT ret ENDPROC(flush_icache_range) ENDPROC(__flush_cache_user_range) /* * __flush_dcache_area(kaddr, size) * * Ensure that the data held in the page kaddr is written back to the * page in question. * * - kaddr - kernel address * - size - size in question */ ENTRY(__flush_dcache_area) dcache_line_size x2, x3 add x1, x0, x1 sub x3, x2, #1 bic x0, x0, x3 1: dc civac, x0 // clean & invalidate D line / unified line add x0, x0, x2 cmp x0, x1 b.lo 1b dsb sy ret ENDPIPROC(__flush_dcache_area) /* * __inval_cache_range(start, end) * - start - start address of region * - end - end address of region */ ENTRY(__inval_cache_range) /* FALLTHROUGH */ /* * __dma_inv_range(start, end) * - start - virtual start address of region * - end - virtual end address of region */ __dma_inv_range: dcache_line_size x2, x3 sub x3, x2, #1 tst x1, x3 // end cache line aligned? bic x1, x1, x3 b.eq 1f dc civac, x1 // clean & invalidate D / U line 1: tst x0, x3 // start cache line aligned? bic x0, x0, x3 b.eq 2f dc civac, x0 // clean & invalidate D / U line b 3f 2: dc ivac, x0 // invalidate D / U line 3: add x0, x0, x2 cmp x0, x1 b.lo 2b dsb sy ret ENDPIPROC(__inval_cache_range) ENDPROC(__dma_inv_range) /* * __dma_clean_range(start, end) * - start - virtual start address of region * - end - virtual end address of region */ __dma_clean_range: dcache_line_size x2, x3 sub x3, x2, #1 bic x0, x0, x3 1: alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE dc cvac, x0 alternative_else dc civac, x0 alternative_endif add x0, x0, x2 cmp x0, x1 b.lo 1b dsb sy ret ENDPROC(__dma_clean_range) /* * __dma_flush_range(start, end) * - start - virtual start address of region * - end - virtual end address of region */ ENTRY(__dma_flush_range) dcache_line_size x2, x3 sub x3, x2, #1 bic x0, x0, x3 1: dc civac, x0 // clean & invalidate D / U line add x0, x0, x2 cmp x0, x1 b.lo 1b dsb sy ret ENDPIPROC(__dma_flush_range) /* * __dma_map_area(start, size, dir) * - start - kernel virtual start address * - size - size of region * - dir - DMA direction */ ENTRY(__dma_map_area) add x1, x1, x0 cmp w2, #DMA_FROM_DEVICE b.eq __dma_inv_range b __dma_clean_range ENDPIPROC(__dma_map_area) /* * __dma_unmap_area(start, size, dir) * - start - kernel virtual start address * - size - size of region * - dir - DMA direction */ ENTRY(__dma_unmap_area) add x1, x1, x0 cmp w2, #DMA_TO_DEVICE b.ne __dma_inv_range ret ENDPIPROC(__dma_unmap_area) |