Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 | /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/syscore_ops.h> #include <asm/proc-fns.h> #include "pmc.h" #define PMC_MAX_IDS 128 #define PMC_MAX_PCKS 8 int of_at91_get_clk_range(struct device_node *np, const char *propname, struct clk_range *range) { u32 min, max; int ret; ret = of_property_read_u32_index(np, propname, 0, &min); if (ret) return ret; ret = of_property_read_u32_index(np, propname, 1, &max); if (ret) return ret; if (range) { range->min = min; range->max = max; } return 0; } EXPORT_SYMBOL_GPL(of_at91_get_clk_range); #ifdef CONFIG_PM static struct regmap *pmcreg; static u8 registered_ids[PMC_MAX_IDS]; static u8 registered_pcks[PMC_MAX_PCKS]; static struct { u32 scsr; u32 pcsr0; u32 uckr; u32 mor; u32 mcfr; u32 pllar; u32 mckr; u32 usb; u32 imr; u32 pcsr1; u32 pcr[PMC_MAX_IDS]; u32 audio_pll0; u32 audio_pll1; u32 pckr[PMC_MAX_PCKS]; } pmc_cache; /* * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored * without alteration in the table, and 0 is for unused clocks. */ void pmc_register_id(u8 id) { int i; for (i = 0; i < PMC_MAX_IDS; i++) { if (registered_ids[i] == 0) { registered_ids[i] = id; break; } if (registered_ids[i] == id) break; } } /* * As Programmable Clock 0 is valid on AT91 chips, there is an offset * of 1 between the stored value and the real clock ID. */ void pmc_register_pck(u8 pck) { int i; for (i = 0; i < PMC_MAX_PCKS; i++) { if (registered_pcks[i] == 0) { registered_pcks[i] = pck + 1; break; } if (registered_pcks[i] == (pck + 1)) break; } } static int pmc_suspend(void) { int i; u8 num; regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr); regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0); regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr); regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor); regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr); regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar); regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr); regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb); regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr); regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1); for (i = 0; registered_ids[i]; i++) { regmap_write(pmcreg, AT91_PMC_PCR, (registered_ids[i] & AT91_PMC_PCR_PID_MASK)); regmap_read(pmcreg, AT91_PMC_PCR, &pmc_cache.pcr[registered_ids[i]]); } for (i = 0; registered_pcks[i]; i++) { num = registered_pcks[i] - 1; regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]); } return 0; } static bool pmc_ready(unsigned int mask) { unsigned int status; regmap_read(pmcreg, AT91_PMC_SR, &status); return ((status & mask) == mask) ? 1 : 0; } static void pmc_resume(void) { int i; u8 num; u32 tmp; u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA; regmap_read(pmcreg, AT91_PMC_MCKR, &tmp); if (pmc_cache.mckr != tmp) pr_warn("MCKR was not configured properly by the firmware\n"); regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp); if (pmc_cache.pllar != tmp) pr_warn("PLLAR was not configured properly by the firmware\n"); regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr); regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0); regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr); regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor); regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr); regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb); regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr); regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1); for (i = 0; registered_ids[i]; i++) { regmap_write(pmcreg, AT91_PMC_PCR, pmc_cache.pcr[registered_ids[i]] | AT91_PMC_PCR_CMD); } for (i = 0; registered_pcks[i]; i++) { num = registered_pcks[i] - 1; regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]); } if (pmc_cache.uckr & AT91_PMC_UPLLEN) mask |= AT91_PMC_LOCKU; while (!pmc_ready(mask)) cpu_relax(); } static struct syscore_ops pmc_syscore_ops = { .suspend = pmc_suspend, .resume = pmc_resume, }; static const struct of_device_id sama5d2_pmc_dt_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { /* sentinel */ } }; static int __init pmc_register_ops(void) { struct device_node *np; np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); pmcreg = syscon_node_to_regmap(np); if (IS_ERR(pmcreg)) return PTR_ERR(pmcreg); register_syscore_ops(&pmc_syscore_ops); return 0; } /* This has to happen before arch_initcall because of the tcb_clksrc driver */ postcore_initcall(pmc_register_ops); #endif |