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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 | /* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ /** * This file defines external dependencies of Display Core. */ #ifndef __DM_SERVICES_H__ #define __DM_SERVICES_H__ /* TODO: remove when DC is complete. */ #include "dm_services_types.h" #include "logger_interface.h" #include "link_service_types.h" #undef DEPRECATED irq_handler_idx dm_register_interrupt( struct dc_context *ctx, struct dc_interrupt_params *int_params, interrupt_handler ih, void *handler_args); /* * * GPU registers access * */ /* enable for debugging new code, this adds 50k to the driver size. */ /* #define DM_CHECK_ADDR_0 */ #define dm_read_reg(ctx, address) \ dm_read_reg_func(ctx, address, __func__) static inline uint32_t dm_read_reg_func( const struct dc_context *ctx, uint32_t address, const char *func_name) { uint32_t value; #ifdef DM_CHECK_ADDR_0 if (address == 0) { DC_ERR("invalid register read; address = 0\n"); return 0; } #endif value = cgs_read_register(ctx->cgs_device, address); return value; } #define dm_write_reg(ctx, address, value) \ dm_write_reg_func(ctx, address, value, __func__) static inline void dm_write_reg_func( const struct dc_context *ctx, uint32_t address, uint32_t value, const char *func_name) { #ifdef DM_CHECK_ADDR_0 if (address == 0) { DC_ERR("invalid register write. address = 0"); return; } #endif cgs_write_register(ctx->cgs_device, address, value); } static inline uint32_t dm_read_index_reg( const struct dc_context *ctx, enum cgs_ind_reg addr_space, uint32_t index) { return cgs_read_ind_register(ctx->cgs_device, addr_space, index); } static inline void dm_write_index_reg( const struct dc_context *ctx, enum cgs_ind_reg addr_space, uint32_t index, uint32_t value) { cgs_write_ind_register(ctx->cgs_device, addr_space, index, value); } static inline uint32_t get_reg_field_value_ex( uint32_t reg_value, uint32_t mask, uint8_t shift) { return (mask & reg_value) >> shift; } #define get_reg_field_value(reg_value, reg_name, reg_field)\ get_reg_field_value_ex(\ (reg_value),\ reg_name ## __ ## reg_field ## _MASK,\ reg_name ## __ ## reg_field ## __SHIFT) static inline uint32_t set_reg_field_value_ex( uint32_t reg_value, uint32_t value, uint32_t mask, uint8_t shift) { ASSERT(mask != 0); return (reg_value & ~mask) | (mask & (value << shift)); } #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ (reg_value) = set_reg_field_value_ex(\ (reg_value),\ (value),\ reg_name ## __ ## reg_field ## _MASK,\ reg_name ## __ ## reg_field ## __SHIFT) uint32_t generic_reg_update_ex(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); #define FD(reg_field) reg_field ## __SHIFT, \ reg_field ## _MASK /* * return number of poll before condition is met * return 0 if condition is not meet after specified time out tries */ unsigned int generic_reg_wait(const struct dc_context *ctx, uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, const char *func_name, int line); /* These macros need to be used with soc15 registers in order to retrieve * the actual offset. */ #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) #define dm_read_reg_soc15(ctx, reg, inst_offset) \ dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ dm_read_reg_func(ctx, mm##reg_name + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + inst_offset, __func__), \ n, __VA_ARGS__) #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ n, __VA_ARGS__) #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ get_reg_field_value_ex(\ (reg_value),\ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ (reg_value) = set_reg_field_value_ex(\ (reg_value),\ (value),\ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) /************************************** * Power Play (PP) interfaces **************************************/ /* Gets valid clocks levels from pplib * * input: clk_type - display clk / sclk / mem clk * * output: array of valid clock levels for given type in ascending order, * with invalid levels filtered out * */ bool dm_pp_get_clock_levels_by_type( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels *clk_level_info); bool dm_pp_get_clock_levels_by_type_with_latency( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels_with_latency *clk_level_info); bool dm_pp_get_clock_levels_by_type_with_voltage( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels_with_voltage *clk_level_info); bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); void dm_pp_get_funcs_rv(struct dc_context *ctx, struct pp_smu_funcs_rv *funcs); /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. * * If the clocks are higher than before, then PP does nothing. * * If the clocks are lower than before, then PP reduces the voltage. * * \returns true - call is successful * false - call failed */ bool dm_pp_apply_display_requirements( const struct dc_context *ctx, const struct dm_pp_display_configuration *pp_display_cfg); bool dm_pp_apply_power_level_change_request( const struct dc_context *ctx, struct dm_pp_power_level_change_request *level_change_req); bool dm_pp_apply_clock_for_voltage_request( const struct dc_context *ctx, struct dm_pp_clock_for_voltage_req *clock_for_voltage_req); bool dm_pp_get_static_clocks( const struct dc_context *ctx, struct dm_pp_static_clock_info *static_clk_info); /****** end of PP interfaces ******/ struct persistent_data_flag { bool save_per_link; bool save_per_edid; }; /* Call to write data in registry editor for persistent data storage. * * \inputs sink - identify edid/link for registry folder creation * module name - identify folders for registry * key name - identify keys within folders for registry * params - value to write in defined folder/key * size - size of the input params * flag - determine whether to save by link or edid * * \returns true - call is successful * false - call failed * * sink module key * ----------------------------------------------------------------------------- * NULL NULL NULL - failure * NULL NULL - - create key with param value * under base folder * NULL - NULL - create module folder under base folder * - NULL NULL - failure * NULL - - - create key under module folder * with no edid/link identification * - NULL - - create key with param value * under base folder * - - NULL - create module folder under base folder * - - - - create key under module folder * with edid/link identification */ bool dm_write_persistent_data(struct dc_context *ctx, const struct dc_sink *sink, const char *module_name, const char *key_name, void *params, unsigned int size, struct persistent_data_flag *flag); /* Call to read data in registry editor for persistent data storage. * * \inputs sink - identify edid/link for registry folder creation * module name - identify folders for registry * key name - identify keys within folders for registry * size - size of the output params * flag - determine whether it was save by link or edid * * \returns params - value read from defined folder/key * true - call is successful * false - call failed * * sink module key * ----------------------------------------------------------------------------- * NULL NULL NULL - failure * NULL NULL - - read key under base folder * NULL - NULL - failure * - NULL NULL - failure * NULL - - - read key under module folder * with no edid/link identification * - NULL - - read key under base folder * - - NULL - failure * - - - - read key under module folder * with edid/link identification */ bool dm_read_persistent_data(struct dc_context *ctx, const struct dc_sink *sink, const char *module_name, const char *key_name, void *params, unsigned int size, struct persistent_data_flag *flag); bool dm_query_extended_brightness_caps (struct dc_context *ctx, enum dm_acpi_display_type display, struct dm_acpi_atif_backlight_caps *pCaps); bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); /* * * print-out services * */ #define dm_log_to_buffer(buffer, size, fmt, args)\ vsnprintf(buffer, size, fmt, args) static inline unsigned long long dm_get_timestamp(struct dc_context *ctx) { return ktime_get_raw_ns(); } unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx, unsigned long long current_time_stamp, unsigned long long last_time_stamp); /* * performance tracing */ void dm_perf_trace_timestamp(const char *func_name, unsigned int line); #define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__) /* * Debug and verification hooks */ void dm_dtn_log_begin(struct dc_context *ctx); void dm_dtn_log_append_v(struct dc_context *ctx, const char *msg, ...); void dm_dtn_log_end(struct dc_context *ctx); #endif /* __DM_SERVICES_H__ */ |