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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 | /* * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include <dt-bindings/clock/berlin2q.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" / { model = "Marvell Armada 1500 pro (BG2-Q) SoC"; compatible = "marvell,berlin2q", "marvell,berlin"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; }; cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; reg = <2>; }; cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; reg = <3>; }; }; refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xf7000000 0x1000000>; interrupt-parent = <&gic>; sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip CLKID_SDIO1XIN>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sdhci1: sdhci@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; clocks = <&chip CLKID_SDIO1XIN>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sdhci2: sdhci@ab1000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; clock-names = "io", "core"; status = "disabled"; }; l2: l2-cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-level = <2>; }; scu: snoop-control-unit@ad0000 { compatible = "arm,cortex-a9-scu"; reg = <0xad0000 0x58>; }; local-timer@ad0600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; clocks = <&chip CLKID_TWD>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; }; gic: interrupt-controller@ad1000 { compatible = "arm,cortex-a9-gic"; reg = <0xad1000 0x1000>, <0xad0100 0x100>; interrupt-controller; #interrupt-cells = <3>; }; apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; gpio0: gpio@0400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; #size-cells = <0>; porta: gpio-port@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0>; }; }; gpio1: gpio@0800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; #size-cells = <0>; portb: gpio-port@1 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <1>; }; }; gpio2: gpio@0c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; #size-cells = <0>; portc: gpio-port@2 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <2>; }; }; gpio3: gpio@1000 { compatible = "snps,dw-apb-gpio"; reg = <0x1000 0x400>; #address-cells = <1>; #size-cells = <0>; portd: gpio-port@3 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <3>; }; }; timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; interrupts = <8>; }; timer1: timer@2c14 { compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer2: timer@2c28 { compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer3: timer@2c3c { compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer4: timer@2c50 { compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer5: timer@2c64 { compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer6: timer@2c78 { compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer7: timer@2c8c { compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; aic: interrupt-controller@3800 { compatible = "snps,dw-apb-ictl"; reg = <0x3800 0x30>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; }; }; chip: chip-control@ea0000 { compatible = "marvell,berlin2q-chip-ctrl"; #clock-cells = <1>; reg = <0xea0000 0x400>, <0xdd0170 0x10>; clocks = <&refclk>; clock-names = "refclk"; }; apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; sm_gpio1: gpio@5000 { compatible = "snps,dw-apb-gpio"; reg = <0x5000 0x400>; #address-cells = <1>; #size-cells = <0>; portf: gpio-port@5 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; }; }; uart0: uart@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; interrupt-parent = <&sic>; interrupts = <8>; clocks = <&refclk>; reg-shift = <2>; pinctrl-0 = <&uart0_pmux>; pinctrl-names = "default"; status = "disabled"; }; uart1: uart@a000 { compatible = "snps,dw-apb-uart"; reg = <0xa000 0x100>; interrupt-parent = <&sic>; interrupts = <9>; clocks = <&refclk>; reg-shift = <2>; pinctrl-0 = <&uart1_pmux>; pinctrl-names = "default"; status = "disabled"; }; sm_gpio0: gpio@c000 { compatible = "snps,dw-apb-gpio"; reg = <0xc000 0x400>; #address-cells = <1>; #size-cells = <0>; porte: gpio-port@4 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; }; }; sysctrl: pin-controller@d000 { compatible = "marvell,berlin2q-system-ctrl"; reg = <0xd000 0x100>; uart0_pmux: uart0-pmux { groups = "GSM12"; function = "uart0"; }; uart1_pmux: uart1-pmux { groups = "GSM14"; function = "uart1"; }; }; sic: interrupt-controller@e000 { compatible = "snps,dw-apb-ictl"; reg = <0xe000 0x30>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; }; }; }; }; |