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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 | #ifndef __timer_defs_h #define __timer_defs_h /* * This file is autogenerated from * file: ../../inst/timer/rtl/timer_regs.r * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp * last modfied: Mon Apr 11 16:09:53 2005 * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r * id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- */ /* Main access macros */ #ifndef REG_RD #define REG_RD( scope, inst, reg ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR #define REG_WR( scope, inst, reg, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_VECT #define REG_RD_VECT( scope, inst, reg, index ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_VECT #define REG_WR_VECT( scope, inst, reg, index, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT #define REG_RD_INT( scope, inst, reg ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR_INT #define REG_WR_INT( scope, inst, reg, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT_VECT #define REG_RD_INT_VECT( scope, inst, reg, index ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_INT_VECT #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_TYPE_CONV #define REG_TYPE_CONV( type, orgtype, val ) \ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) #endif #ifndef reg_page_size #define reg_page_size 8192 #endif #ifndef REG_ADDR #define REG_ADDR( scope, inst, reg ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_ADDR_VECT #define REG_ADDR_VECT( scope, inst, reg, index ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif /* C-code for register scope timer */ /* Register rw_tmr0_div, scope timer, type rw */ typedef unsigned int reg_timer_rw_tmr0_div; #define REG_RD_ADDR_timer_rw_tmr0_div 0 #define REG_WR_ADDR_timer_rw_tmr0_div 0 /* Register r_tmr0_data, scope timer, type r */ typedef unsigned int reg_timer_r_tmr0_data; #define REG_RD_ADDR_timer_r_tmr0_data 4 /* Register rw_tmr0_ctrl, scope timer, type rw */ typedef struct { unsigned int op : 2; unsigned int freq : 3; unsigned int dummy1 : 27; } reg_timer_rw_tmr0_ctrl; #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 /* Register rw_tmr1_div, scope timer, type rw */ typedef unsigned int reg_timer_rw_tmr1_div; #define REG_RD_ADDR_timer_rw_tmr1_div 16 #define REG_WR_ADDR_timer_rw_tmr1_div 16 /* Register r_tmr1_data, scope timer, type r */ typedef unsigned int reg_timer_r_tmr1_data; #define REG_RD_ADDR_timer_r_tmr1_data 20 /* Register rw_tmr1_ctrl, scope timer, type rw */ typedef struct { unsigned int op : 2; unsigned int freq : 3; unsigned int dummy1 : 27; } reg_timer_rw_tmr1_ctrl; #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 /* Register rs_cnt_data, scope timer, type rs */ typedef struct { unsigned int tmr : 24; unsigned int cnt : 8; } reg_timer_rs_cnt_data; #define REG_RD_ADDR_timer_rs_cnt_data 32 /* Register r_cnt_data, scope timer, type r */ typedef struct { unsigned int tmr : 24; unsigned int cnt : 8; } reg_timer_r_cnt_data; #define REG_RD_ADDR_timer_r_cnt_data 36 /* Register rw_cnt_cfg, scope timer, type rw */ typedef struct { unsigned int clk : 2; unsigned int dummy1 : 30; } reg_timer_rw_cnt_cfg; #define REG_RD_ADDR_timer_rw_cnt_cfg 40 #define REG_WR_ADDR_timer_rw_cnt_cfg 40 /* Register rw_trig, scope timer, type rw */ typedef unsigned int reg_timer_rw_trig; #define REG_RD_ADDR_timer_rw_trig 48 #define REG_WR_ADDR_timer_rw_trig 48 /* Register rw_trig_cfg, scope timer, type rw */ typedef struct { unsigned int tmr : 2; unsigned int dummy1 : 30; } reg_timer_rw_trig_cfg; #define REG_RD_ADDR_timer_rw_trig_cfg 52 #define REG_WR_ADDR_timer_rw_trig_cfg 52 /* Register r_time, scope timer, type r */ typedef unsigned int reg_timer_r_time; #define REG_RD_ADDR_timer_r_time 56 /* Register rw_out, scope timer, type rw */ typedef struct { unsigned int tmr : 2; unsigned int dummy1 : 30; } reg_timer_rw_out; #define REG_RD_ADDR_timer_rw_out 60 #define REG_WR_ADDR_timer_rw_out 60 /* Register rw_wd_ctrl, scope timer, type rw */ typedef struct { unsigned int cnt : 8; unsigned int cmd : 1; unsigned int key : 7; unsigned int dummy1 : 16; } reg_timer_rw_wd_ctrl; #define REG_RD_ADDR_timer_rw_wd_ctrl 64 #define REG_WR_ADDR_timer_rw_wd_ctrl 64 /* Register r_wd_stat, scope timer, type r */ typedef struct { unsigned int cnt : 8; unsigned int cmd : 1; unsigned int dummy1 : 23; } reg_timer_r_wd_stat; #define REG_RD_ADDR_timer_r_wd_stat 68 /* Register rw_intr_mask, scope timer, type rw */ typedef struct { unsigned int tmr0 : 1; unsigned int tmr1 : 1; unsigned int cnt : 1; unsigned int trig : 1; unsigned int dummy1 : 28; } reg_timer_rw_intr_mask; #define REG_RD_ADDR_timer_rw_intr_mask 72 #define REG_WR_ADDR_timer_rw_intr_mask 72 /* Register rw_ack_intr, scope timer, type rw */ typedef struct { unsigned int tmr0 : 1; unsigned int tmr1 : 1; unsigned int cnt : 1; unsigned int trig : 1; unsigned int dummy1 : 28; } reg_timer_rw_ack_intr; #define REG_RD_ADDR_timer_rw_ack_intr 76 #define REG_WR_ADDR_timer_rw_ack_intr 76 /* Register r_intr, scope timer, type r */ typedef struct { unsigned int tmr0 : 1; unsigned int tmr1 : 1; unsigned int cnt : 1; unsigned int trig : 1; unsigned int dummy1 : 28; } reg_timer_r_intr; #define REG_RD_ADDR_timer_r_intr 80 /* Register r_masked_intr, scope timer, type r */ typedef struct { unsigned int tmr0 : 1; unsigned int tmr1 : 1; unsigned int cnt : 1; unsigned int trig : 1; unsigned int dummy1 : 28; } reg_timer_r_masked_intr; #define REG_RD_ADDR_timer_r_masked_intr 84 /* Register rw_test, scope timer, type rw */ typedef struct { unsigned int dis : 1; unsigned int en : 1; unsigned int dummy1 : 30; } reg_timer_rw_test; #define REG_RD_ADDR_timer_rw_test 88 #define REG_WR_ADDR_timer_rw_test 88 /* Constants */ enum { regk_timer_ext = 0x00000001, regk_timer_f100 = 0x00000007, regk_timer_f29_493 = 0x00000004, regk_timer_f32 = 0x00000005, regk_timer_f32_768 = 0x00000006, regk_timer_hold = 0x00000001, regk_timer_ld = 0x00000000, regk_timer_no = 0x00000000, regk_timer_off = 0x00000000, regk_timer_run = 0x00000002, regk_timer_rw_cnt_cfg_default = 0x00000000, regk_timer_rw_intr_mask_default = 0x00000000, regk_timer_rw_out_default = 0x00000000, regk_timer_rw_test_default = 0x00000000, regk_timer_rw_tmr0_ctrl_default = 0x00000000, regk_timer_rw_tmr1_ctrl_default = 0x00000000, regk_timer_rw_trig_cfg_default = 0x00000000, regk_timer_start = 0x00000001, regk_timer_stop = 0x00000000, regk_timer_time = 0x00000001, regk_timer_tmr0 = 0x00000002, regk_timer_tmr1 = 0x00000003, regk_timer_yes = 0x00000001 }; #endif /* __timer_defs_h */ |