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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 | #ifndef __iop_dmc_in_defs_h #define __iop_dmc_in_defs_h /* * This file is autogenerated from * file: ../../inst/io_proc/rtl/iop_dmc_in.r * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp * last modfied: Mon Apr 11 16:08:45 2005 * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- */ /* Main access macros */ #ifndef REG_RD #define REG_RD( scope, inst, reg ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR #define REG_WR( scope, inst, reg, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_VECT #define REG_RD_VECT( scope, inst, reg, index ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_VECT #define REG_WR_VECT( scope, inst, reg, index, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT #define REG_RD_INT( scope, inst, reg ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR_INT #define REG_WR_INT( scope, inst, reg, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT_VECT #define REG_RD_INT_VECT( scope, inst, reg, index ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_INT_VECT #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_TYPE_CONV #define REG_TYPE_CONV( type, orgtype, val ) \ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) #endif #ifndef reg_page_size #define reg_page_size 8192 #endif #ifndef REG_ADDR #define REG_ADDR( scope, inst, reg ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_ADDR_VECT #define REG_ADDR_VECT( scope, inst, reg, index ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif /* C-code for register scope iop_dmc_in */ /* Register rw_cfg, scope iop_dmc_in, type rw */ typedef struct { unsigned int sth_intr : 3; unsigned int last_dis_dif : 1; unsigned int dummy1 : 28; } reg_iop_dmc_in_rw_cfg; #define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 #define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 /* Register rw_ctrl, scope iop_dmc_in, type rw */ typedef struct { unsigned int dif_en : 1; unsigned int dif_dis : 1; unsigned int stream_clr : 1; unsigned int dummy1 : 29; } reg_iop_dmc_in_rw_ctrl; #define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 #define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 /* Register r_stat, scope iop_dmc_in, type r */ typedef struct { unsigned int dif_en : 1; unsigned int dummy1 : 31; } reg_iop_dmc_in_r_stat; #define REG_RD_ADDR_iop_dmc_in_r_stat 8 /* Register rw_stream_cmd, scope iop_dmc_in, type rw */ typedef struct { unsigned int cmd : 10; unsigned int dummy1 : 6; unsigned int n : 8; unsigned int dummy2 : 8; } reg_iop_dmc_in_rw_stream_cmd; #define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 #define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 /* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; #define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 #define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 /* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; #define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 #define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 /* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ typedef struct { unsigned int eop : 1; unsigned int wait : 1; unsigned int keep_md : 1; unsigned int size : 3; unsigned int dummy1 : 26; } reg_iop_dmc_in_rw_stream_ctrl; #define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 #define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 /* Register r_stream_stat, scope iop_dmc_in, type r */ typedef struct { unsigned int sth : 7; unsigned int dummy1 : 9; unsigned int full : 1; unsigned int last_pkt : 1; unsigned int data_md_valid : 1; unsigned int ctxt_md_valid : 1; unsigned int group_md_valid : 1; unsigned int stream_busy : 1; unsigned int cmd_rdy : 1; unsigned int dummy2 : 9; } reg_iop_dmc_in_r_stream_stat; #define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 /* Register r_data_descr, scope iop_dmc_in, type r */ typedef struct { unsigned int ctrl : 8; unsigned int stat : 8; unsigned int md : 16; } reg_iop_dmc_in_r_data_descr; #define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 /* Register r_ctxt_descr, scope iop_dmc_in, type r */ typedef struct { unsigned int ctrl : 8; unsigned int stat : 8; unsigned int md0 : 16; } reg_iop_dmc_in_r_ctxt_descr; #define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 /* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; #define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 /* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; #define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 /* Register r_group_descr, scope iop_dmc_in, type r */ typedef struct { unsigned int ctrl : 8; unsigned int stat : 8; unsigned int md : 16; } reg_iop_dmc_in_r_group_descr; #define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 /* Register rw_data_descr, scope iop_dmc_in, type rw */ typedef struct { unsigned int dummy1 : 16; unsigned int md : 16; } reg_iop_dmc_in_rw_data_descr; #define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 #define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 /* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ typedef struct { unsigned int dummy1 : 16; unsigned int md0 : 16; } reg_iop_dmc_in_rw_ctxt_descr; #define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 #define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 /* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; #define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 #define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 /* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; #define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 #define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 /* Register rw_group_descr, scope iop_dmc_in, type rw */ typedef struct { unsigned int dummy1 : 16; unsigned int md : 16; } reg_iop_dmc_in_rw_group_descr; #define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 #define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 /* Register rw_intr_mask, scope iop_dmc_in, type rw */ typedef struct { unsigned int data_md : 1; unsigned int ctxt_md : 1; unsigned int group_md : 1; unsigned int cmd_rdy : 1; unsigned int sth : 1; unsigned int full : 1; unsigned int dummy1 : 26; } reg_iop_dmc_in_rw_intr_mask; #define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 #define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 /* Register rw_ack_intr, scope iop_dmc_in, type rw */ typedef struct { unsigned int data_md : 1; unsigned int ctxt_md : 1; unsigned int group_md : 1; unsigned int cmd_rdy : 1; unsigned int sth : 1; unsigned int full : 1; unsigned int dummy1 : 26; } reg_iop_dmc_in_rw_ack_intr; #define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 #define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 /* Register r_intr, scope iop_dmc_in, type r */ typedef struct { unsigned int data_md : 1; unsigned int ctxt_md : 1; unsigned int group_md : 1; unsigned int cmd_rdy : 1; unsigned int sth : 1; unsigned int full : 1; unsigned int dummy1 : 26; } reg_iop_dmc_in_r_intr; #define REG_RD_ADDR_iop_dmc_in_r_intr 96 /* Register r_masked_intr, scope iop_dmc_in, type r */ typedef struct { unsigned int data_md : 1; unsigned int ctxt_md : 1; unsigned int group_md : 1; unsigned int cmd_rdy : 1; unsigned int sth : 1; unsigned int full : 1; unsigned int dummy1 : 26; } reg_iop_dmc_in_r_masked_intr; #define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 /* Constants */ enum { regk_iop_dmc_in_ack_pkt = 0x00000100, regk_iop_dmc_in_array = 0x00000008, regk_iop_dmc_in_burst = 0x00000020, regk_iop_dmc_in_copy_next = 0x00000010, regk_iop_dmc_in_copy_up = 0x00000020, regk_iop_dmc_in_dis_c = 0x00000010, regk_iop_dmc_in_dis_g = 0x00000020, regk_iop_dmc_in_lim1 = 0x00000000, regk_iop_dmc_in_lim16 = 0x00000004, regk_iop_dmc_in_lim2 = 0x00000001, regk_iop_dmc_in_lim32 = 0x00000005, regk_iop_dmc_in_lim4 = 0x00000002, regk_iop_dmc_in_lim64 = 0x00000006, regk_iop_dmc_in_lim8 = 0x00000003, regk_iop_dmc_in_load_c = 0x00000200, regk_iop_dmc_in_load_c_n = 0x00000280, regk_iop_dmc_in_load_c_next = 0x00000240, regk_iop_dmc_in_load_d = 0x00000140, regk_iop_dmc_in_load_g = 0x00000300, regk_iop_dmc_in_load_g_down = 0x000003c0, regk_iop_dmc_in_load_g_next = 0x00000340, regk_iop_dmc_in_load_g_up = 0x00000380, regk_iop_dmc_in_next_en = 0x00000010, regk_iop_dmc_in_next_pkt = 0x00000010, regk_iop_dmc_in_no = 0x00000000, regk_iop_dmc_in_restore = 0x00000020, regk_iop_dmc_in_rw_cfg_default = 0x00000000, regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, regk_iop_dmc_in_rw_data_descr_default = 0x00000000, regk_iop_dmc_in_rw_group_descr_default = 0x00000000, regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, regk_iop_dmc_in_save_down = 0x00000020, regk_iop_dmc_in_save_up = 0x00000020, regk_iop_dmc_in_set_reg = 0x00000050, regk_iop_dmc_in_set_w_size1 = 0x00000190, regk_iop_dmc_in_set_w_size2 = 0x000001a0, regk_iop_dmc_in_set_w_size4 = 0x000001c0, regk_iop_dmc_in_store_c = 0x00000002, regk_iop_dmc_in_store_descr = 0x00000000, regk_iop_dmc_in_store_g = 0x00000004, regk_iop_dmc_in_store_md = 0x00000001, regk_iop_dmc_in_update_down = 0x00000020, regk_iop_dmc_in_yes = 0x00000001 }; #endif /* __iop_dmc_in_defs_h */ |