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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 | /* * Static Memory Controller for AT32 chips * * Copyright (C) 2006 Atmel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #define DEBUG #include <linux/clk.h> #include <linux/err.h> #include <linux/init.h> #include <linux/module.h> #include <linux/platform_device.h> #include <asm/io.h> #include <asm/arch/smc.h> #include "hsmc.h" #define NR_CHIP_SELECTS 6 struct hsmc { void __iomem *regs; struct clk *pclk; struct clk *mck; }; static struct hsmc *hsmc; int smc_set_configuration(int cs, const struct smc_config *config) { unsigned long mul; unsigned long offset; u32 setup, pulse, cycle, mode; if (!hsmc) return -ENODEV; if (cs >= NR_CHIP_SELECTS) return -EINVAL; /* * cycles = x / T = x * f * = ((x * 1000000000) * ((f * 65536) / 1000000000)) / 65536 * = ((x * 1000000000) * (((f / 10000) * 65536) / 100000)) / 65536 */ mul = (clk_get_rate(hsmc->mck) / 10000) << 16; mul /= 100000; #define ns2cyc(x) ((((x) * mul) + 65535) >> 16) setup = (HSMC_BF(NWE_SETUP, ns2cyc(config->nwe_setup)) | HSMC_BF(NCS_WR_SETUP, ns2cyc(config->ncs_write_setup)) | HSMC_BF(NRD_SETUP, ns2cyc(config->nrd_setup)) | HSMC_BF(NCS_RD_SETUP, ns2cyc(config->ncs_read_setup))); pulse = (HSMC_BF(NWE_PULSE, ns2cyc(config->nwe_pulse)) | HSMC_BF(NCS_WR_PULSE, ns2cyc(config->ncs_write_pulse)) | HSMC_BF(NRD_PULSE, ns2cyc(config->nrd_pulse)) | HSMC_BF(NCS_RD_PULSE, ns2cyc(config->ncs_read_pulse))); cycle = (HSMC_BF(NWE_CYCLE, ns2cyc(config->write_cycle)) | HSMC_BF(NRD_CYCLE, ns2cyc(config->read_cycle))); switch (config->bus_width) { case 1: mode = HSMC_BF(DBW, HSMC_DBW_8_BITS); break; case 2: mode = HSMC_BF(DBW, HSMC_DBW_16_BITS); break; case 4: mode = HSMC_BF(DBW, HSMC_DBW_32_BITS); break; default: return -EINVAL; } if (config->nrd_controlled) mode |= HSMC_BIT(READ_MODE); if (config->nwe_controlled) mode |= HSMC_BIT(WRITE_MODE); if (config->byte_write) mode |= HSMC_BIT(BAT); pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n", cs, setup, pulse, cycle, mode); offset = cs * 0x10; hsmc_writel(hsmc, SETUP0 + offset, setup); hsmc_writel(hsmc, PULSE0 + offset, pulse); hsmc_writel(hsmc, CYCLE0 + offset, cycle); hsmc_writel(hsmc, MODE0 + offset, mode); hsmc_readl(hsmc, MODE0); /* I/O barrier */ return 0; } EXPORT_SYMBOL(smc_set_configuration); static int hsmc_probe(struct platform_device *pdev) { struct resource *regs; struct clk *pclk, *mck; int ret; if (hsmc) return -EBUSY; regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!regs) return -ENXIO; pclk = clk_get(&pdev->dev, "pclk"); if (IS_ERR(pclk)) return PTR_ERR(pclk); mck = clk_get(&pdev->dev, "mck"); if (IS_ERR(mck)) { ret = PTR_ERR(mck); goto out_put_pclk; } ret = -ENOMEM; hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL); if (!hsmc) goto out_put_clocks; clk_enable(pclk); clk_enable(mck); hsmc->pclk = pclk; hsmc->mck = mck; hsmc->regs = ioremap(regs->start, regs->end - regs->start + 1); if (!hsmc->regs) goto out_disable_clocks; dev_info(&pdev->dev, "Atmel Static Memory Controller at 0x%08lx\n", (unsigned long)regs->start); platform_set_drvdata(pdev, hsmc); return 0; out_disable_clocks: clk_disable(mck); clk_disable(pclk); kfree(hsmc); out_put_clocks: clk_put(mck); out_put_pclk: clk_put(pclk); hsmc = NULL; return ret; } static struct platform_driver hsmc_driver = { .probe = hsmc_probe, .driver = { .name = "smc", }, }; static int __init hsmc_init(void) { return platform_driver_register(&hsmc_driver); } arch_initcall(hsmc_init); |