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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 | /* * include/asm-x86_64/xor.h * * Optimized RAID-5 checksumming functions for MMX and SSE. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * You should have received a copy of the GNU General Public License * (for example /usr/src/linux/COPYING); if not, write to the Free * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* * Cache avoiding checksumming functions utilizing KNI instructions * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo) */ /* * Based on * High-speed RAID5 checksumming functions utilizing SSE instructions. * Copyright (C) 1998 Ingo Molnar. */ /* * x86-64 changes / gcc fixes from Andi Kleen. * Copyright 2002 Andi Kleen, SuSE Labs. * * This hasn't been optimized for the hammer yet, but there are likely * no advantages to be gotten from x86-64 here anyways. */ typedef struct { unsigned long a,b; } __attribute__((aligned(16))) xmm_store_t; /* Doesn't use gcc to save the XMM registers, because there is no easy way to tell it to do a clts before the register saving. */ #define XMMS_SAVE do { \ preempt_disable(); \ asm volatile ( \ "movq %%cr0,%0 ;\n\t" \ "clts ;\n\t" \ "movups %%xmm0,(%1) ;\n\t" \ "movups %%xmm1,0x10(%1) ;\n\t" \ "movups %%xmm2,0x20(%1) ;\n\t" \ "movups %%xmm3,0x30(%1) ;\n\t" \ : "=&r" (cr0) \ : "r" (xmm_save) \ : "memory"); \ } while(0) #define XMMS_RESTORE do { \ asm volatile ( \ "sfence ;\n\t" \ "movups (%1),%%xmm0 ;\n\t" \ "movups 0x10(%1),%%xmm1 ;\n\t" \ "movups 0x20(%1),%%xmm2 ;\n\t" \ "movups 0x30(%1),%%xmm3 ;\n\t" \ "movq %0,%%cr0 ;\n\t" \ : \ : "r" (cr0), "r" (xmm_save) \ : "memory"); \ preempt_enable(); \ } while(0) #define OFFS(x) "16*("#x")" #define PF_OFFS(x) "256+16*("#x")" #define PF0(x) " prefetchnta "PF_OFFS(x)"(%[p1]) ;\n" #define LD(x,y) " movaps "OFFS(x)"(%[p1]), %%xmm"#y" ;\n" #define ST(x,y) " movaps %%xmm"#y", "OFFS(x)"(%[p1]) ;\n" #define PF1(x) " prefetchnta "PF_OFFS(x)"(%[p2]) ;\n" #define PF2(x) " prefetchnta "PF_OFFS(x)"(%[p3]) ;\n" #define PF3(x) " prefetchnta "PF_OFFS(x)"(%[p4]) ;\n" #define PF4(x) " prefetchnta "PF_OFFS(x)"(%[p5]) ;\n" #define PF5(x) " prefetchnta "PF_OFFS(x)"(%[p6]) ;\n" #define XO1(x,y) " xorps "OFFS(x)"(%[p2]), %%xmm"#y" ;\n" #define XO2(x,y) " xorps "OFFS(x)"(%[p3]), %%xmm"#y" ;\n" #define XO3(x,y) " xorps "OFFS(x)"(%[p4]), %%xmm"#y" ;\n" #define XO4(x,y) " xorps "OFFS(x)"(%[p5]), %%xmm"#y" ;\n" #define XO5(x,y) " xorps "OFFS(x)"(%[p6]), %%xmm"#y" ;\n" static void xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) { unsigned int lines = bytes >> 8; unsigned long cr0; xmm_store_t xmm_save[4]; XMMS_SAVE; asm volatile ( #undef BLOCK #define BLOCK(i) \ LD(i,0) \ LD(i+1,1) \ PF1(i) \ PF1(i+2) \ LD(i+2,2) \ LD(i+3,3) \ PF0(i+4) \ PF0(i+6) \ XO1(i,0) \ XO1(i+1,1) \ XO1(i+2,2) \ XO1(i+3,3) \ ST(i,0) \ ST(i+1,1) \ ST(i+2,2) \ ST(i+3,3) \ PF0(0) PF0(2) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addq %[inc], %[p1] ;\n" " addq %[inc], %[p2] ;\n" " decl %[cnt] ; jnz 1b" : [p1] "+r" (p1), [p2] "+r" (p2), [cnt] "+r" (lines) : [inc] "r" (256UL) : "memory"); XMMS_RESTORE; } static void xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3) { unsigned int lines = bytes >> 8; xmm_store_t xmm_save[4]; unsigned long cr0; XMMS_SAVE; __asm__ __volatile__ ( #undef BLOCK #define BLOCK(i) \ PF1(i) \ PF1(i+2) \ LD(i,0) \ LD(i+1,1) \ LD(i+2,2) \ LD(i+3,3) \ PF2(i) \ PF2(i+2) \ PF0(i+4) \ PF0(i+6) \ XO1(i,0) \ XO1(i+1,1) \ XO1(i+2,2) \ XO1(i+3,3) \ XO2(i,0) \ XO2(i+1,1) \ XO2(i+2,2) \ XO2(i+3,3) \ ST(i,0) \ ST(i+1,1) \ ST(i+2,2) \ ST(i+3,3) \ PF0(0) PF0(2) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addq %[inc], %[p1] ;\n" " addq %[inc], %[p2] ;\n" " addq %[inc], %[p3] ;\n" " decl %[cnt] ; jnz 1b" : [cnt] "+r" (lines), [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3) : [inc] "r" (256UL) : "memory"); XMMS_RESTORE; } static void xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3, unsigned long *p4) { unsigned int lines = bytes >> 8; xmm_store_t xmm_save[4]; unsigned long cr0; XMMS_SAVE; __asm__ __volatile__ ( #undef BLOCK #define BLOCK(i) \ PF1(i) \ PF1(i+2) \ LD(i,0) \ LD(i+1,1) \ LD(i+2,2) \ LD(i+3,3) \ PF2(i) \ PF2(i+2) \ XO1(i,0) \ XO1(i+1,1) \ XO1(i+2,2) \ XO1(i+3,3) \ PF3(i) \ PF3(i+2) \ PF0(i+4) \ PF0(i+6) \ XO2(i,0) \ XO2(i+1,1) \ XO2(i+2,2) \ XO2(i+3,3) \ XO3(i,0) \ XO3(i+1,1) \ XO3(i+2,2) \ XO3(i+3,3) \ ST(i,0) \ ST(i+1,1) \ ST(i+2,2) \ ST(i+3,3) \ PF0(0) PF0(2) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addq %[inc], %[p1] ;\n" " addq %[inc], %[p2] ;\n" " addq %[inc], %[p3] ;\n" " addq %[inc], %[p4] ;\n" " decl %[cnt] ; jnz 1b" : [cnt] "+c" (lines), [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4) : [inc] "r" (256UL) : "memory" ); XMMS_RESTORE; } static void xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3, unsigned long *p4, unsigned long *p5) { unsigned int lines = bytes >> 8; xmm_store_t xmm_save[4]; unsigned long cr0; XMMS_SAVE; __asm__ __volatile__ ( #undef BLOCK #define BLOCK(i) \ PF1(i) \ PF1(i+2) \ LD(i,0) \ LD(i+1,1) \ LD(i+2,2) \ LD(i+3,3) \ PF2(i) \ PF2(i+2) \ XO1(i,0) \ XO1(i+1,1) \ XO1(i+2,2) \ XO1(i+3,3) \ PF3(i) \ PF3(i+2) \ XO2(i,0) \ XO2(i+1,1) \ XO2(i+2,2) \ XO2(i+3,3) \ PF4(i) \ PF4(i+2) \ PF0(i+4) \ PF0(i+6) \ XO3(i,0) \ XO3(i+1,1) \ XO3(i+2,2) \ XO3(i+3,3) \ XO4(i,0) \ XO4(i+1,1) \ XO4(i+2,2) \ XO4(i+3,3) \ ST(i,0) \ ST(i+1,1) \ ST(i+2,2) \ ST(i+3,3) \ PF0(0) PF0(2) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addq %[inc], %[p1] ;\n" " addq %[inc], %[p2] ;\n" " addq %[inc], %[p3] ;\n" " addq %[inc], %[p4] ;\n" " addq %[inc], %[p5] ;\n" " decl %[cnt] ; jnz 1b" : [cnt] "+c" (lines), [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4), [p5] "+r" (p5) : [inc] "r" (256UL) : "memory"); XMMS_RESTORE; } static struct xor_block_template xor_block_sse = { .name = "generic_sse", .do_2 = xor_sse_2, .do_3 = xor_sse_3, .do_4 = xor_sse_4, .do_5 = xor_sse_5, }; #undef XOR_TRY_TEMPLATES #define XOR_TRY_TEMPLATES \ do { \ xor_speed(&xor_block_sse); \ } while (0) /* We force the use of the SSE xor block because it can write around L2. We may also be able to load into the L1 only depending on how the cpu deals with a load to a line that is being prefetched. */ #define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse) |