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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 | /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Format of an instruction in memory. * * Copyright (C) 1996 by Ralf Baechle */ #ifndef _ASM_INST_H #define _ASM_INST_H /* * Major opcodes; before MIPS IV cop1x was called cop3. */ enum major_op { spec_op, bcond_op, j_op, jal_op, beq_op, bne_op, blez_op, bgtz_op, addi_op, addiu_op, slti_op, sltiu_op, andi_op, ori_op, xori_op, lui_op, cop0_op, cop1_op, cop2_op, cop1x_op, beql_op, bnel_op, blezl_op, bgtzl_op, daddi_op, daddiu_op, ldl_op, ldr_op, major_1c_op, major_1d_op, major_1e_op, major_1f_op, lb_op, lh_op, lwl_op, lw_op, lbu_op, lhu_op, lwr_op, lwu_op, sb_op, sh_op, swl_op, sw_op, sdl_op, sdr_op, swr_op, cache_op, ll_op, lwc1_op, lwc2_op, pref_op, lld_op, ldc1_op, ldc2_op, ld_op, sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */ scd_op, sdc1_op, sdc2_op, sd_op }; /* * func field of spec opcode. */ enum spec_op { sll_op, movc_op, srl_op, sra_op, sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ jr_op, jalr_op, movz_op, movn_op, syscall_op, break_op, spim_op, sync_op, mfhi_op, mthi_op, mflo_op, mtlo_op, dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, mult_op, multu_op, div_op, divu_op, dmult_op, dmultu_op, ddiv_op, ddivu_op, add_op, addu_op, sub_op, subu_op, and_op, or_op, xor_op, nor_op, spec3_unused_op, spec4_unused_op, slt_op, sltu_op, dadd_op, daddu_op, dsub_op, dsubu_op, tge_op, tgeu_op, tlt_op, tltu_op, teq_op, spec5_unused_op, tne_op, spec6_unused_op, dsll_op, spec7_unused_op, dsrl_op, dsra_op, dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op }; /* * rt field of bcond opcodes. */ enum rt_op { bltz_op, bgez_op, bltzl_op, bgezl_op, spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, tgei_op, tgeiu_op, tlti_op, tltiu_op, teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, bltzal_op, bgezal_op, bltzall_op, bgezall_op /* * The others (0x14 - 0x1f) are unused. */ }; /* * rs field of cop opcodes. */ enum cop_op { mfc_op = 0x00, dmfc_op = 0x01, cfc_op = 0x02, mtc_op = 0x04, dmtc_op = 0x05, ctc_op = 0x06, bc_op = 0x08, cop_op = 0x10, copm_op = 0x18 }; /* * func field of cop0 coi opcodes. */ enum cop0_coi_func { tlbr_op = 0x01, tlbwi_op = 0x02, tlbwr_op = 0x06, tlbp_op = 0x08, rfe_op = 0x10, eret_op = 0x18 }; /* * func field of cop0 com opcodes. */ enum cop0_com_func { tlbr1_op = 0x01, tlbw_op = 0x02, tlbp1_op = 0x08, dctr_op = 0x09, dctw_op = 0x0a }; /* * fmt field of cop1 opcodes. */ enum cop1_fmt { s_fmt, d_fmt, e_fmt, q_fmt, w_fmt, l_fmt }; /* * func field of cop1 instructions using d, s or w format. */ enum cop1_sdw_func { fadd_op = 0x00, fsub_op = 0x01, fmul_op = 0x02, fdiv_op = 0x03, fsqrt_op = 0x04, fabs_op = 0x05, fmov_op = 0x06, fneg_op = 0x07, froundl_op = 0x08, ftruncl_op = 0x09, fceill_op = 0x0a, ffloorl_op = 0x0b, fround_op = 0x0c, ftrunc_op = 0x0d, fceil_op = 0x0e, ffloor_op = 0x0f, fmovc_op = 0x11, fmovz_op = 0x12, fmovn_op = 0x13, frecip_op = 0x15, frsqrt_op = 0x16, fcvts_op = 0x20, fcvtd_op = 0x21, fcvte_op = 0x22, fcvtw_op = 0x24, fcvtl_op = 0x25, fcmp_op = 0x30 }; /* * func field of cop1x opcodes (MIPS IV). */ enum cop1x_func { lwxc1_op = 0x00, ldxc1_op = 0x01, pfetch_op = 0x07, swxc1_op = 0x08, sdxc1_op = 0x09, madd_s_op = 0x20, madd_d_op = 0x21, madd_e_op = 0x22, msub_s_op = 0x28, msub_d_op = 0x29, msub_e_op = 0x2a, nmadd_s_op = 0x30, nmadd_d_op = 0x31, nmadd_e_op = 0x32, nmsub_s_op = 0x38, nmsub_d_op = 0x39, nmsub_e_op = 0x3a }; /* * func field for mad opcodes (MIPS IV). */ enum mad_func { madd_op = 0x08, msub_op = 0x0a, nmadd_op = 0x0c, nmsub_op = 0x0e }; /* * Damn ... bitfields depend from byteorder :-( */ #ifdef __MIPSEB__ struct j_format { /* Jump format */ unsigned int opcode : 6; unsigned int target : 26; }; struct i_format { /* Immediate format (addi, lw, ...) */ unsigned int opcode : 6; unsigned int rs : 5; unsigned int rt : 5; signed int simmediate : 16; }; struct u_format { /* Unsigned immediate format (ori, xori, ...) */ unsigned int opcode : 6; unsigned int rs : 5; unsigned int rt : 5; unsigned int uimmediate : 16; }; struct c_format { /* Cache (>= R6000) format */ unsigned int opcode : 6; unsigned int rs : 5; unsigned int c_op : 3; unsigned int cache : 2; unsigned int simmediate : 16; }; struct r_format { /* Register format */ unsigned int opcode : 6; unsigned int rs : 5; unsigned int rt : 5; unsigned int rd : 5; unsigned int re : 5; unsigned int func : 6; }; struct p_format { /* Performance counter format (R10000) */ unsigned int opcode : 6; unsigned int rs : 5; unsigned int rt : 5; unsigned int rd : 5; unsigned int re : 5; unsigned int func : 6; }; struct f_format { /* FPU register format */ unsigned int opcode : 6; unsigned int : 1; unsigned int fmt : 4; unsigned int rt : 5; unsigned int rd : 5; unsigned int re : 5; unsigned int func : 6; }; struct ma_format { /* FPU multipy and add format (MIPS IV) */ unsigned int opcode : 6; unsigned int fr : 5; unsigned int ft : 5; unsigned int fs : 5; unsigned int fd : 5; unsigned int func : 4; unsigned int fmt : 2; }; #elif defined(__MIPSEL__) struct j_format { /* Jump format */ unsigned int target : 26; unsigned int opcode : 6; }; struct i_format { /* Immediate format */ signed int simmediate : 16; unsigned int rt : 5; unsigned int rs : 5; unsigned int opcode : 6; }; struct u_format { /* Unsigned immediate format */ unsigned int uimmediate : 16; unsigned int rt : 5; unsigned int rs : 5; unsigned int opcode : 6; }; struct c_format { /* Cache (>= R6000) format */ unsigned int simmediate : 16; unsigned int cache : 2; unsigned int c_op : 3; unsigned int rs : 5; unsigned int opcode : 6; }; struct r_format { /* Register format */ unsigned int func : 6; unsigned int re : 5; unsigned int rd : 5; unsigned int rt : 5; unsigned int rs : 5; unsigned int opcode : 6; }; struct p_format { /* Performance counter format (R10000) */ unsigned int func : 6; unsigned int re : 5; unsigned int rd : 5; unsigned int rt : 5; unsigned int rs : 5; unsigned int opcode : 6; }; struct f_format { /* FPU register format */ unsigned int func : 6; unsigned int re : 5; unsigned int rd : 5; unsigned int rt : 5; unsigned int fmt : 4; unsigned int : 1; unsigned int opcode : 6; }; struct ma_format { /* FPU multipy and add format (MIPS IV) */ unsigned int fmt : 2; unsigned int func : 4; unsigned int fd : 5; unsigned int fs : 5; unsigned int ft : 5; unsigned int fr : 5; unsigned int opcode : 6; }; #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" #endif union mips_instruction { unsigned int word; unsigned short halfword[2]; unsigned char byte[4]; struct j_format j_format; struct i_format i_format; struct u_format u_format; struct c_format c_format; struct r_format r_format; struct f_format f_format; struct ma_format ma_format; }; #endif /* _ASM_INST_H */ |