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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 | /* * r2300_switch.S: R2300 specific task switching code. * * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle * Copyright (C) 1994, 1995, 1996 by Andreas Busse * * Multi-cpu abstraction and macros for easier reading: * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * * Further modifications to make this work: * Copyright (c) 1998-2000 Harald Koerfgen */ #include <asm/asm.h> #include <asm/bootinfo.h> #include <asm/cachectl.h> #include <asm/current.h> #include <asm/fpregdef.h> #include <asm/mipsregs.h> #include <asm/offset.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/processor.h> #include <asm/regdef.h> #include <asm/stackframe.h> #include <asm/asmmacro.h> .set mips1 .align 5 /* * task_struct *resume(task_struct *prev, * task_struct *next) */ LEAF(resume) #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif mfc0 t1, CP0_STATUS sw t1, THREAD_STATUS(a0) CPU_SAVE_NONSCRATCH(a0) sw ra, THREAD_REG31(a0) /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. */ move $28, a1 CPU_RESTORE_NONSCRATCH($28) addiu t0, $28, KERNEL_STACK_SIZE-32 sw t0, kernelsp mfc0 t1, CP0_STATUS /* Do we really need this? */ li a3, 0xff00 and t1, a3 lw a2, THREAD_STATUS($28) nor a3, $0, a3 and a2, a3 or a2, t1 mtc0 a2, CP0_STATUS .set noreorder jr ra move v0, a0 .set reorder END(resume) /* * Do lazy fpu context switch. Saves FPU context to the process in a0 * and loads the new context of the current process. */ #define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) LEAF(lazy_fpu_switch) mfc0 t0, CP0_STATUS # enable cp1 li t3, 0x20000000 or t0, t3 mtc0 t0, CP0_STATUS .set noreorder beqz a0, 2f # Save floating point state nor t3, zero, t3 .set reorder lw t1, ST_OFF(a0) # last thread looses fpu and t1, t3 sw t1, ST_OFF(a0) FPU_SAVE_SINGLE(a0, t1) # clobbers t1 2: FPU_RESTORE_SINGLE($28, t0) # clobbers t0 jr ra END(lazy_fpu_switch) /* * Save a thread's fp context. */ LEAF(save_fp) FPU_SAVE_SINGLE(a0, t1) # clobbers t1 jr ra END(save_fp) /* * Restore a thread's fp context. */ LEAF(restore_fp) FPU_RESTORE_SINGLE(a0, t1) # clobbers t1 jr ra END(restore_fp) /* * Load the FPU with signalling NANS. This bit pattern we're using has * the property that no matter wether considered as single or as double * precission represents signaling NANS. * * We initialize fcr31 to rounding to nearest, no exceptions. */ #define FPU_DEFAULT 0x00000000 LEAF(init_fpu) mfc0 t0, CP0_STATUS li t1, 0x20000000 or t0, t1 mtc0 t0, CP0_STATUS li t1, FPU_DEFAULT ctc1 t1, fcr31 li t0, -1 mtc1 t0, $f0 mtc1 t0, $f1 mtc1 t0, $f2 mtc1 t0, $f3 mtc1 t0, $f4 mtc1 t0, $f5 mtc1 t0, $f6 mtc1 t0, $f7 mtc1 t0, $f8 mtc1 t0, $f9 mtc1 t0, $f10 mtc1 t0, $f11 mtc1 t0, $f12 mtc1 t0, $f13 mtc1 t0, $f14 mtc1 t0, $f15 mtc1 t0, $f16 mtc1 t0, $f17 mtc1 t0, $f18 mtc1 t0, $f19 mtc1 t0, $f20 mtc1 t0, $f21 mtc1 t0, $f22 mtc1 t0, $f23 mtc1 t0, $f24 mtc1 t0, $f25 mtc1 t0, $f26 mtc1 t0, $f27 mtc1 t0, $f28 mtc1 t0, $f29 mtc1 t0, $f30 .set noreorder jr ra mtc1 t0, $f31 .set reorder END(init_fpu) |