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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 | /*********************************************************************** * Copyright 2001 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * * arch/mips/kernel/time.c * Common time service routines for MIPS machines. See * Documents/MIPS/time.txt. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. *********************************************************************** */ #include <linux/config.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/sched.h> #include <linux/param.h> #include <linux/time.h> #include <linux/smp.h> #include <linux/kernel_stat.h> #include <linux/spinlock.h> #include <linux/interrupt.h> #include <asm/bootinfo.h> #include <asm/cpu.h> #include <asm/time.h> #include <asm/hardirq.h> /* * macro for catching spurious errors. Eable to LL_DEBUG in kernel hacking * config menu. */ #ifdef CONFIG_LL_DEBUG #define MIPS_ASSERT(x) if (!(x)) { panic("MIPS_ASSERT failed at %s:%d\n", __FILE__, __LINE__); } #define MIPS_DEBUG(x) do { x; } while (0) #else #define MIPS_ASSERT(x) #define MIPS_DEBUG(x) #endif /* This is for machines which generate the exact clock. */ #define USECS_PER_JIFFY (1000000/HZ) #define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff) /* * forward reference */ extern rwlock_t xtime_lock; extern volatile unsigned long wall_jiffies; /* * By default we provide the null RTC ops */ static unsigned long null_rtc_get_time(void) { return mktime(2000, 1, 1, 0, 0, 0); } static int null_rtc_set_time(unsigned long sec) { return 0; } unsigned long (*rtc_get_time)(void) = null_rtc_get_time; int (*rtc_set_time)(unsigned long) = null_rtc_set_time; /* * timeofday services, for syscalls. */ void do_gettimeofday(struct timeval *tv) { unsigned long flags; read_lock_irqsave (&xtime_lock, flags); *tv = xtime; tv->tv_usec += do_gettimeoffset(); /* * xtime is atomically updated in timer_bh. jiffies - wall_jiffies * is nonzero if the timer bottom half hasnt executed yet. */ if (jiffies - wall_jiffies) tv->tv_usec += USECS_PER_JIFFY; read_unlock_irqrestore (&xtime_lock, flags); if (tv->tv_usec >= 1000000) { tv->tv_usec -= 1000000; tv->tv_sec++; } } void do_settimeofday(struct timeval *tv) { write_lock_irq (&xtime_lock); /* This is revolting. We need to set the xtime.tv_usec * correctly. However, the value in this location is * is value at the last tick. * Discover what correction gettimeofday * would have done, and then undo it! */ tv->tv_usec -= do_gettimeoffset(); if (tv->tv_usec < 0) { tv->tv_usec += 1000000; tv->tv_sec--; } xtime = *tv; time_adjust = 0; /* stop active adjtime() */ time_status |= STA_UNSYNC; time_maxerror = NTP_PHASE_LIMIT; time_esterror = NTP_PHASE_LIMIT; write_unlock_irq (&xtime_lock); } /* * Gettimeoffset routines. These routines returns the time duration * since last timer interrupt in usecs. * * If the exact CPU counter frequency is known, use fixed_rate_gettimeoffset. * Otherwise use calibrate_gettimeoffset() * * If the CPU does not have counter register all, you can either supply * your own gettimeoffset() routine, or use null_gettimeoffset() routines, * which gives the same resolution as HZ. */ /* This is for machines which generate the exact clock. */ #define USECS_PER_JIFFY (1000000/HZ) /* usecs per counter cycle, shifted to left by 32 bits */ static unsigned int sll32_usecs_per_cycle=0; /* how many counter cycles in a jiffy */ static unsigned long cycles_per_jiffy=0; /* Cycle counter value at the previous timer interrupt.. */ static unsigned int timerhi, timerlo; /* last time when xtime and rtc are sync'ed up */ static long last_rtc_update; /* the function pointer to one of the gettimeoffset funcs*/ unsigned long (*do_gettimeoffset)(void) = null_gettimeoffset; unsigned long null_gettimeoffset(void) { return 0; } unsigned long fixed_rate_gettimeoffset(void) { u32 count; unsigned long res; MIPS_ASSERT(mips_cpu.options & MIPS_CPU_COUNTER); MIPS_ASSERT(mips_counter_frequency != 0); MIPS_ASSERT(sll32_usecs_per_cycle != 0); /* Get last timer tick in absolute kernel time */ count = read_32bit_cp0_register(CP0_COUNT); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; __asm__("multu\t%1,%2\n\t" "mfhi\t%0" :"=r" (res) :"r" (count), "r" (sll32_usecs_per_cycle)); /* * Due to possible jiffies inconsistencies, we need to check * the result so that we'll get a timer that is monotonic. */ if (res >= USECS_PER_JIFFY) res = USECS_PER_JIFFY-1; return res; } /* * Cached "1/(clocks per usec)*2^32" value. * It has to be recalculated once each jiffy. */ static unsigned long cached_quotient; /* Last jiffy when calibrate_divXX_gettimeoffset() was called. */ static unsigned long last_jiffies = 0; /* * copied from include/asm/div64. * We do the copy instead of include the header file because we don't * want to reply on _MIPS_ISA value. */ #define do_div64_32(res, high, low, base) ({ \ unsigned long __quot, __mod; \ unsigned long __cf, __tmp, __i; \ \ __asm__(".set push\n\t" \ ".set noat\n\t" \ ".set noreorder\n\t" \ "b 1f\n\t" \ " li %4,0x21\n" \ "0:\n\t" \ "sll $1,%0,0x1\n\t" \ "srl %3,%0,0x1f\n\t" \ "or %0,$1,$2\n\t" \ "sll %1,%1,0x1\n\t" \ "sll %2,%2,0x1\n" \ "1:\n\t" \ "bnez %3,2f\n\t" \ "sltu $2,%0,%z5\n\t" \ "bnez $2,3f\n\t" \ "2:\n\t" \ " addiu %4,%4,-1\n\t" \ "subu %0,%0,%z5\n\t" \ "addiu %2,%2,1\n" \ "3:\n\t" \ "bnez %4,0b\n\t" \ " srl $2,%1,0x1f\n\t" \ ".set pop" \ : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \ "=&r" (__i) \ : "Jr" (base), "0" (high), "1" (low), "2" (0), "3" (0) \ /* Aarrgh! Ran out of gcc's limit on constraints... */ \ : "$1", "$2"); \ \ (res) = __quot; \ __mod; }) /* * This is copied from dec/time.c:do_ioasic_gettimeoffset() by Mercij. */ unsigned long calibrate_div32_gettimeoffset(void) { u32 count; unsigned long res, tmp; unsigned long quotient; MIPS_ASSERT(mips_cpu.options & MIPS_CPU_COUNTER); tmp = jiffies; quotient = cached_quotient; if (last_jiffies != tmp) { last_jiffies = tmp; if (last_jiffies != 0) { unsigned long r0; do_div64_32(r0, timerhi, timerlo, tmp); do_div64_32(quotient, USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0); cached_quotient = quotient; } } /* Get last timer tick in absolute kernel time */ count = read_32bit_cp0_register(CP0_COUNT); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; __asm__("multu %2,%3" : "=l" (tmp), "=h" (res) : "r" (count), "r" (quotient)); /* * Due to possible jiffies inconsistencies, we need to check * the result so that we'll get a timer that is monotonic. */ if (res >= USECS_PER_JIFFY) res = USECS_PER_JIFFY - 1; return res; } unsigned long calibrate_div64_gettimeoffset(void) { u32 count; unsigned long res, tmp; unsigned long quotient; MIPS_ASSERT(mips_cpu.options & MIPS_CPU_COUNTER); MIPS_ASSERT((mips_cpu.isa_level != MIPS_CPU_ISA_I) && (mips_cpu.isa_level != MIPS_CPU_ISA_II) && (mips_cpu.isa_level != MIPS_CPU_ISA_M32)); tmp = jiffies; quotient = cached_quotient; if (tmp && last_jiffies != tmp) { last_jiffies = tmp; __asm__(".set\tnoreorder\n\t" ".set\tnoat\n\t" ".set\tmips3\n\t" "lwu\t%0,%2\n\t" "dsll32\t$1,%1,0\n\t" "or\t$1,$1,%0\n\t" "ddivu\t$0,$1,%3\n\t" "mflo\t$1\n\t" "dsll32\t%0,%4,0\n\t" "nop\n\t" "ddivu\t$0,%0,$1\n\t" "mflo\t%0\n\t" ".set\tmips0\n\t" ".set\tat\n\t" ".set\treorder" :"=&r" (quotient) :"r" (timerhi), "m" (timerlo), "r" (tmp), "r" (USECS_PER_JIFFY) :"$1"); cached_quotient = quotient; } /* Get last timer tick in absolute kernel time */ count = read_32bit_cp0_register(CP0_COUNT); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; __asm__("multu\t%1,%2\n\t" "mfhi\t%0" :"=r" (res) :"r" (count), "r" (quotient)); /* * Due to possible jiffies inconsistencies, we need to check * the result so that we'll get a timer that is monotonic. */ if (res >= USECS_PER_JIFFY) res = USECS_PER_JIFFY-1; return res; } /* * high-level timer interrupt service routines. This function * is set as irqaction->handler and is invoked through do_IRQ. */ void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { if (mips_cpu.options & MIPS_CPU_COUNTER) { unsigned int count; /* * The cycle counter is only 32 bit which is good for about * a minute at current count rates of upto 150MHz or so. */ count = read_32bit_cp0_register(CP0_COUNT); timerhi += (count < timerlo); /* Wrap around */ timerlo = count; /* * set up for next timer interrupt - no harm if the machine * is using another timer interrupt source. * Note that writing to COMPARE register clears the interrupt */ write_32bit_cp0_register (CP0_COMPARE, count + cycles_per_jiffy); } if(!user_mode(regs)) { if (prof_buffer && current->pid) { extern int _stext; unsigned long pc = regs->cp0_epc; pc -= (unsigned long) &_stext; pc >>= prof_shift; /* * Dont ignore out-of-bounds pc values silently, * put them into the last histogram slot, so if * present, they will show up as a sharp peak. */ if (pc > prof_len-1) pc = prof_len-1; atomic_inc((atomic_t *)&prof_buffer[pc]); } } /* * call the generic timer interrupt handling */ do_timer(regs); /* * If we have an externally synchronized Linux clock, then update * CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be * called as close as possible to 500 ms before the new second starts. */ read_lock (&xtime_lock); if ((time_status & STA_UNSYNC) == 0 && xtime.tv_sec > last_rtc_update + 660 && xtime.tv_usec >= 500000 - ((unsigned) tick) / 2 && xtime.tv_usec <= 500000 + ((unsigned) tick) / 2) { if (rtc_set_time(xtime.tv_sec) == 0) { last_rtc_update = xtime.tv_sec; } else { last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ } } read_unlock (&xtime_lock); /* * If jiffies has overflowed in this timer_interrupt we must * update the timer[hi]/[lo] to make fast gettimeoffset funcs * quotient calc still valid. -arca */ if (!jiffies) { timerhi = timerlo = 0; } } asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs) { int cpu = smp_processor_id(); irq_enter(cpu, irq); kstat.irqs[cpu][irq]++; /* we keep interrupt disabled all the time */ timer_interrupt(irq, NULL, regs); irq_exit(cpu, irq); /* check for bottom half */ if (softirq_active(cpu)&softirq_mask(cpu)) do_softirq(); } /* * time_init() - it does the following things. * * 1) board_time_init() - * a) (optional) set up RTC routines, * b) (optional) calibrate and set the mips_counter_frequency * (only needed if you intended to use fixed_rate_gettimeoffset * or use cpu counter as timer interrupt source) * 2) setup xtime based on rtc_get_time(). * 3) choose a appropriate gettimeoffset routine. * 4) calculate a couple of cached variables for later usage * 5) board_timer_setup() - * a) (optional) over-write any choices made above by time_init(). * b) machine specific code should setup the timer irqaction. * c) enable the timer interrupt */ void (*board_time_init)(void) = NULL; void (*board_timer_setup)(struct irqaction *irq) = NULL; unsigned int mips_counter_frequency = 0; static struct irqaction timer_irqaction = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL}; void __init time_init(void) { printk("New MIPS time_init() invoked.\n"); if (board_time_init) board_time_init(); /* setup xtime */ write_lock_irq(&xtime_lock); xtime.tv_sec = rtc_get_time(); xtime.tv_usec = 0; write_unlock_irq(&xtime_lock); /* choose appropriate gettimeoffset routine */ if ( ! (mips_cpu.options & MIPS_CPU_COUNTER) ) { /* no cpu counter - sorry */ do_gettimeoffset = null_gettimeoffset; } else if (mips_counter_frequency != 0) { /* we have cpu counter and know counter frequency! */ do_gettimeoffset = fixed_rate_gettimeoffset; } else if ((mips_cpu.isa_level == MIPS_CPU_ISA_M32) || (mips_cpu.isa_level == MIPS_CPU_ISA_I) || (mips_cpu.isa_level == MIPS_CPU_ISA_II) ) { /* we need to calibrate the counter but we don't have * 64-bit division. */ do_gettimeoffset = calibrate_div32_gettimeoffset; } else { /* we need to calibrate the counter but we *do* have * 64-bit division. */ do_gettimeoffset = calibrate_div64_gettimeoffset; } /* caclulate cache parameters */ if (mips_counter_frequency) { cycles_per_jiffy = mips_counter_frequency / HZ; /* sll32_usecs_per_cycle = 10^6 * 2^32 / mips_counter_freq */ /* any better way to do this? */ sll32_usecs_per_cycle = mips_counter_frequency / 100000; sll32_usecs_per_cycle = 0xffffffff / sll32_usecs_per_cycle; sll32_usecs_per_cycle *= 10; MIPS_DEBUG(printk("cycles_per_jiffy = %d\n", cycles_per_jiffy)); MIPS_DEBUG(printk("sll32_usecs_per_cycle = %d \n", sll32_usecs_per_cycle)); } /* * Call board specific timer interrupt setup. * * this pointer must be setup in machine setup routine. * * Even if the machine choose to use low-level timer interrupt, * it still needs to setup the timer_irqaction. * In that case, it might be better to set timer_irqaction.handler * to be NULL function so that we are sure the high-level code * is not invoked accidentally. */ MIPS_ASSERT(board_timer_setup != NULL); board_timer_setup(&timer_irqaction); } |