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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 | /* * BRIEF MODULE DESCRIPTION * Au1000 interrupt routines. * * Copyright 2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/errno.h> #include <linux/init.h> #include <linux/kernel_stat.h> #include <linux/module.h> #include <linux/signal.h> #include <linux/sched.h> #include <linux/types.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/timex.h> #include <linux/slab.h> #include <linux/random.h> #include <linux/delay.h> #include <asm/bitops.h> #include <asm/bootinfo.h> #include <asm/io.h> #include <asm/mipsregs.h> #include <asm/system.h> #include <asm/au1000.h> #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) #undef DEBUG_IRQ #ifdef DEBUG_IRQ /* note: prints function name for you */ #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) #else #define DPRINTK(fmt, args...) #endif #define EXT_INTC0_REQ0 2 /* IP 2 */ #define EXT_INTC0_REQ1 3 /* IP 3 */ #define EXT_INTC1_REQ0 4 /* IP 4 */ #define EXT_INTC1_REQ1 5 /* IP 5 */ #define MIPS_TIMER_IP 7 /* IP 7 */ #ifdef CONFIG_REMOTE_DEBUG extern void breakpoint(void); #endif extern asmlinkage void au1000_IRQ(void); extern void set_debug_traps(void); extern irq_cpustat_t irq_stat []; extern irq_desc_t irq_desc[NR_IRQS]; unsigned int local_bh_count[NR_CPUS]; unsigned int local_irq_count[NR_CPUS]; static void setup_local_irq(unsigned int irq, int type, int int_req); static unsigned int startup_irq(unsigned int irq); static void end_irq(unsigned int irq_nr); static inline void mask_and_ack_level_irq(unsigned int irq_nr); static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr); static inline void local_enable_irq(unsigned int irq_nr); static inline void local_disable_irq(unsigned int irq_nr); unsigned long spurious_interrupts; extern unsigned int do_IRQ(int irq, struct pt_regs *regs); extern void __init init_generic_irq(void); static inline void sync(void) { __asm volatile ("sync"); } /* Function for careful CP0 interrupt mask access */ static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) { unsigned long status = read_32bit_cp0_register(CP0_STATUS); status &= ~((clr_mask & 0xFF) << 8); status |= (set_mask & 0xFF) << 8; write_32bit_cp0_register(CP0_STATUS, status); } static inline void mask_cpu_irq_input(unsigned int irq_nr) { modify_cp0_intmask(irq_nr, 0); } static inline void unmask_cpu_irq_input(unsigned int irq_nr) { modify_cp0_intmask(0, irq_nr); } static void disable_cpu_irq_input(unsigned int irq_nr) { unsigned long flags; save_and_cli(flags); mask_cpu_irq_input(irq_nr); restore_flags(flags); } static void enable_cpu_irq_input(unsigned int irq_nr) { unsigned long flags; save_and_cli(flags); unmask_cpu_irq_input(irq_nr); restore_flags(flags); } static void setup_local_irq(unsigned int irq_nr, int type, int int_req) { /* Config2[n], Config1[n], Config0[n] */ if (irq_nr > AU1000_LAST_INTC0_INT) { switch (type) { case INTC_INT_RISE_EDGE: /* 0:0:1 */ outl(1<<irq_nr,INTC1_CONFIG2_CLEAR); outl(1<<irq_nr, INTC1_CONFIG1_CLEAR); outl(1<<irq_nr, INTC1_CONFIG0_SET); break; case INTC_INT_FALL_EDGE: /* 0:1:0 */ outl(1<<irq_nr, INTC1_CONFIG2_CLEAR); outl(1<<irq_nr, INTC1_CONFIG1_SET); outl(1<<irq_nr, INTC1_CONFIG0_CLEAR); break; case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ outl(1<<irq_nr, INTC1_CONFIG2_SET); outl(1<<irq_nr, INTC1_CONFIG1_CLEAR); outl(1<<irq_nr, INTC1_CONFIG0_SET); break; case INTC_INT_LOW_LEVEL: /* 1:1:0 */ outl(1<<irq_nr, INTC1_CONFIG2_SET); outl(1<<irq_nr, INTC1_CONFIG1_SET); outl(1<<irq_nr, INTC1_CONFIG0_CLEAR); break; case INTC_INT_DISABLED: /* 0:0:0 */ outl(1<<irq_nr, INTC1_CONFIG0_CLEAR); outl(1<<irq_nr, INTC1_CONFIG1_CLEAR); outl(1<<irq_nr, INTC1_CONFIG2_CLEAR); break; default: /* disable the interrupt */ printk("unexpected int type %d (irq %d)\n", type, irq_nr); outl(1<<irq_nr, INTC1_CONFIG0_CLEAR); outl(1<<irq_nr, INTC1_CONFIG1_CLEAR); outl(1<<irq_nr, INTC1_CONFIG2_CLEAR); return; } if (int_req) /* assign to interrupt request 1 */ outl(1<<irq_nr, INTC1_ASSIGN_REQ_CLEAR); else /* assign to interrupt request 0 */ outl(1<<irq_nr, INTC1_ASSIGN_REQ_SET); outl(1<<irq_nr, INTC1_SOURCE_SET); outl(1<<irq_nr, INTC1_MASK_CLEAR); } else { switch (type) { case INTC_INT_RISE_EDGE: /* 0:0:1 */ outl(1<<irq_nr,INTC0_CONFIG2_CLEAR); outl(1<<irq_nr, INTC0_CONFIG1_CLEAR); outl(1<<irq_nr, INTC0_CONFIG0_SET); break; case INTC_INT_FALL_EDGE: /* 0:1:0 */ outl(1<<irq_nr, INTC0_CONFIG2_CLEAR); outl(1<<irq_nr, INTC0_CONFIG1_SET); outl(1<<irq_nr, INTC0_CONFIG0_CLEAR); break; case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ outl(1<<irq_nr, INTC0_CONFIG2_SET); outl(1<<irq_nr, INTC0_CONFIG1_CLEAR); outl(1<<irq_nr, INTC0_CONFIG0_SET); break; case INTC_INT_LOW_LEVEL: /* 1:1:0 */ outl(1<<irq_nr, INTC0_CONFIG2_SET); outl(1<<irq_nr, INTC0_CONFIG1_SET); outl(1<<irq_nr, INTC0_CONFIG0_CLEAR); break; case INTC_INT_DISABLED: /* 0:0:0 */ outl(1<<irq_nr, INTC0_CONFIG0_CLEAR); outl(1<<irq_nr, INTC0_CONFIG1_CLEAR); outl(1<<irq_nr, INTC0_CONFIG2_CLEAR); break; default: /* disable the interrupt */ printk("unexpected int type %d (irq %d)\n", type, irq_nr); outl(1<<irq_nr, INTC0_CONFIG0_CLEAR); outl(1<<irq_nr, INTC0_CONFIG1_CLEAR); outl(1<<irq_nr, INTC0_CONFIG2_CLEAR); return; } if (int_req) /* assign to interrupt request 1 */ outl(1<<irq_nr, INTC0_ASSIGN_REQ_CLEAR); else /* assign to interrupt request 0 */ outl(1<<irq_nr, INTC0_ASSIGN_REQ_SET); outl(1<<irq_nr, INTC0_SOURCE_SET); outl(1<<irq_nr, INTC0_MASK_CLEAR); } sync(); } static unsigned int startup_irq(unsigned int irq_nr) { local_enable_irq(irq_nr); return 0; } static void shutdown_irq(unsigned int irq_nr) { local_disable_irq(irq_nr); return; } static inline void local_enable_irq(unsigned int irq_nr) { if (irq_nr > AU1000_LAST_INTC0_INT) { outl(1<<irq_nr, INTC1_MASK_SET); } else { outl(1<<irq_nr, INTC0_MASK_SET); } sync(); } static inline void local_disable_irq(unsigned int irq_nr) { if (irq_nr > AU1000_LAST_INTC0_INT) { outl(1<<irq_nr, INTC1_MASK_CLEAR); } else { outl(1<<irq_nr, INTC0_MASK_CLEAR); } sync(); } static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) { if (irq_nr > AU1000_LAST_INTC0_INT) { outl(1<<irq_nr, INTC1_R_EDGE_DETECT_CLEAR); outl(1<<irq_nr, INTC1_MASK_CLEAR); } else { outl(1<<irq_nr, INTC0_R_EDGE_DETECT_CLEAR); outl(1<<irq_nr, INTC0_MASK_CLEAR); } sync(); } static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) { if (irq_nr > AU1000_LAST_INTC0_INT) { outl(1<<irq_nr, INTC1_F_EDGE_DETECT_CLEAR); outl(1<<irq_nr, INTC1_MASK_CLEAR); } else { outl(1<<irq_nr, INTC0_F_EDGE_DETECT_CLEAR); outl(1<<irq_nr, INTC0_MASK_CLEAR); } } static inline void mask_and_ack_level_irq(unsigned int irq_nr) { local_disable_irq(irq_nr); sync(); return; } static void end_irq(unsigned int irq_nr) { if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) local_enable_irq(irq_nr); else printk("warning: end_irq %d did not enable\n", irq_nr); } static struct hw_interrupt_type rise_edge_irq_type = { "Au1000 Rise Edge", startup_irq, shutdown_irq, local_enable_irq, local_disable_irq, mask_and_ack_rise_edge_irq, end_irq, NULL }; static struct hw_interrupt_type fall_edge_irq_type = { "Au1000 Fall Edge", startup_irq, shutdown_irq, local_enable_irq, local_disable_irq, mask_and_ack_fall_edge_irq, end_irq, NULL }; static struct hw_interrupt_type level_irq_type = { "Au1000 Level", startup_irq, shutdown_irq, local_enable_irq, local_disable_irq, mask_and_ack_level_irq, end_irq, NULL }; void enable_cpu_timer(void) { enable_cpu_irq_input(1<<MIPS_TIMER_IP); /* timer interrupt */ } void __init init_IRQ(void) { int i; unsigned long cp0_status; cp0_status = read_32bit_cp0_register(CP0_STATUS); memset(irq_desc, 0, sizeof(irq_desc)); set_except_vector(0, au1000_IRQ); init_generic_irq(); /* * Setup high priority interrupts on int_request0; low priority on * int_request1 */ for (i = 0; i <= NR_IRQS; i++) { switch (i) { case AU1000_MAC0_DMA_INT: case AU1000_MAC1_DMA_INT: setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0); irq_desc[i].handler = &level_irq_type; break; default: /* active high, level interrupt */ setup_local_irq(i, INTC_INT_HIGH_LEVEL, 1); irq_desc[i].handler = &level_irq_type; break; } } set_cp0_status(ALLINTS); #ifdef CONFIG_REMOTE_DEBUG /* If local serial I/O used for debug port, enter kgdb at once */ puts("Waiting for kgdb to connect..."); set_debug_traps(); breakpoint(); #endif } void mips_spurious_interrupt(struct pt_regs *regs) { spurious_interrupts++; } void intc0_req0_irqdispatch(struct pt_regs *regs) { int irq = 0, i; unsigned long int_request; int_request = inl(INTC0_REQ0_INT); if (!int_request) return; for (i=0; i<32; i++) { if ((int_request & 0x1)) { do_IRQ(irq, regs); } irq++; int_request >>= 1; } } void intc0_req1_irqdispatch(struct pt_regs *regs) { int irq = 0, i; unsigned long int_request; int_request = inl(INTC0_REQ1_INT); if (!int_request) return; for (i=0; i<32; i++) { if ((int_request & 0x1)) { do_IRQ(irq, regs); } irq++; int_request >>= 1; } } void intc1_req0_irqdispatch(struct pt_regs *regs) { int irq = 0, i; unsigned long int_request; int_request = inl(INTC1_REQ0_INT); if (!int_request) return; for (i=0; i<32; i++) { if ((int_request & 0x1)) { do_IRQ(irq, regs); } irq++; int_request >>= 1; } } void intc1_req1_irqdispatch(struct pt_regs *regs) { int irq = 0, i; unsigned long int_request; int_request = inl(INTC1_REQ1_INT); if (!int_request) return; for (i=0; i<32; i++) { if ((int_request & 0x1)) { do_IRQ(irq, regs); } irq++; int_request >>= 1; } } |