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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 | /* * CHRP pci routines. */ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/delay.h> #include <linux/string.h> #include <linux/init.h> #include <linux/openpic.h> #include <linux/ide.h> #include <asm/io.h> #include <asm/pgtable.h> #include <asm/irq.h> #include <asm/hydra.h> #include <asm/prom.h> #include <asm/gg2.h> #include <asm/machdep.h> #include "pci.h" /* LongTrail */ #define pci_config_addr(bus, dev, offset) \ (GG2_PCI_CONFIG_BASE | ((bus)<<16) | ((dev)<<8) | (offset)) volatile struct Hydra *Hydra = NULL; /* * The VLSI Golden Gate II has only 512K of PCI configuration space, so we * limit the bus number to 3 bits */ int gg2_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char *val) { if (bus > 7) { *val = 0xff; return PCIBIOS_DEVICE_NOT_FOUND; } *val = in_8((unsigned char *)pci_config_addr(bus, dev_fn, offset)); return PCIBIOS_SUCCESSFUL; } int gg2_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short *val) { if (bus > 7) { *val = 0xffff; return PCIBIOS_DEVICE_NOT_FOUND; } *val = in_le16((unsigned short *)pci_config_addr(bus, dev_fn, offset)); return PCIBIOS_SUCCESSFUL; } int gg2_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int *val) { if (bus > 7) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } *val = in_le32((unsigned int *)pci_config_addr(bus, dev_fn, offset)); return PCIBIOS_SUCCESSFUL; } int gg2_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char val) { if (bus > 7) return PCIBIOS_DEVICE_NOT_FOUND; out_8((unsigned char *)pci_config_addr(bus, dev_fn, offset), val); return PCIBIOS_SUCCESSFUL; } int gg2_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short val) { if (bus > 7) return PCIBIOS_DEVICE_NOT_FOUND; out_le16((unsigned short *)pci_config_addr(bus, dev_fn, offset), val); return PCIBIOS_SUCCESSFUL; } int gg2_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int val) { if (bus > 7) return PCIBIOS_DEVICE_NOT_FOUND; out_le32((unsigned int *)pci_config_addr(bus, dev_fn, offset), val); return PCIBIOS_SUCCESSFUL; } #define python_config_address(bus) (unsigned *)((0xfef00000+0xf8000)-(bus*0x100000)) #define python_config_data(bus) ((0xfef00000+0xf8010)-(bus*0x100000)) #define PYTHON_CFA(b, d, o) (0x80 | ((b<<6) << 8) | ((d) << 16) \ | (((o) & ~3) << 24)) unsigned int python_busnr = 0; int python_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char *val) { if (bus > python_busnr) { *val = 0xff; return PCIBIOS_DEVICE_NOT_FOUND; } out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset)); *val = in_8((unsigned char *)python_config_data(bus) + (offset&3)); return PCIBIOS_SUCCESSFUL; } int python_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short *val) { if (bus > python_busnr) { *val = 0xffff; return PCIBIOS_DEVICE_NOT_FOUND; } out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset)); *val = in_le16((unsigned short *)(python_config_data(bus) + (offset&3))); return PCIBIOS_SUCCESSFUL; } int python_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int *val) { if (bus > python_busnr) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset)); *val = in_le32((unsigned *)python_config_data(bus)); return PCIBIOS_SUCCESSFUL; } int python_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char val) { if (bus > python_busnr) return PCIBIOS_DEVICE_NOT_FOUND; out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset)); out_8((volatile unsigned char *)python_config_data(bus) + (offset&3), val); return PCIBIOS_SUCCESSFUL; } int python_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short val) { if (bus > python_busnr) return PCIBIOS_DEVICE_NOT_FOUND; out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset)); out_le16((volatile unsigned short *)python_config_data(bus) + (offset&3), val); return PCIBIOS_SUCCESSFUL; } int python_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int val) { if (bus > python_busnr) return PCIBIOS_DEVICE_NOT_FOUND; out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset)); out_le32((unsigned *)python_config_data(bus) + (offset&3), val); return PCIBIOS_SUCCESSFUL; } int rtas_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char *val) { unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16); if ( call_rtas( "read-pci-config", 2, 2, (ulong *)&val, addr, 1 ) != 0 ) return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_SUCCESSFUL; } int rtas_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short *val) { unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16); if ( call_rtas( "read-pci-config", 2, 2, (ulong *)&val, addr, 2 ) != 0 ) return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_SUCCESSFUL; } int rtas_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int *val) { unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16); if ( call_rtas( "read-pci-config", 2, 2, (ulong *)&val, addr, 4 ) != 0 ) return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_SUCCESSFUL; } int rtas_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char val) { unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16); if ( call_rtas( "write-pci-config", 3, 1, NULL, addr, 1, (ulong)val ) != 0 ) return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_SUCCESSFUL; } int rtas_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short val) { unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16); if ( call_rtas( "write-pci-config", 3, 1, NULL, addr, 2, (ulong)val ) != 0 ) return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_SUCCESSFUL; } int rtas_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int val) { unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16); if ( call_rtas( "write-pci-config", 3, 1, NULL, addr, 4, (ulong)val ) != 0 ) return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_SUCCESSFUL; } /* * Temporary fixes for PCI devices. These should be replaced by OF query * code -- Geert */ static u_char hydra_openpic_initsenses[] __initdata = { 1, /* HYDRA_INT_SIO */ 0, /* HYDRA_INT_SCSI_DMA */ 0, /* HYDRA_INT_SCCA_TX_DMA */ 0, /* HYDRA_INT_SCCA_RX_DMA */ 0, /* HYDRA_INT_SCCB_TX_DMA */ 0, /* HYDRA_INT_SCCB_RX_DMA */ 1, /* HYDRA_INT_SCSI */ 1, /* HYDRA_INT_SCCA */ 1, /* HYDRA_INT_SCCB */ 1, /* HYDRA_INT_VIA */ 1, /* HYDRA_INT_ADB */ 0, /* HYDRA_INT_ADB_NMI */ /* all others are 1 (= default) */ }; int __init hydra_init(void) { struct device_node *np; np = find_devices("mac-io"); if (np == NULL || np->n_addrs == 0) { printk(KERN_WARNING "Warning: no mac-io found\n"); return 0; } Hydra = ioremap(np->addrs[0].address, np->addrs[0].size); printk("Hydra Mac I/O at %x\n", np->addrs[0].address); out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | HYDRA_FC_SCSI_CELL_EN | HYDRA_FC_SCCA_ENABLE | HYDRA_FC_SCCB_ENABLE | HYDRA_FC_ARB_BYPASS | HYDRA_FC_MPIC_ENABLE | HYDRA_FC_SLOW_SCC_PCLK | HYDRA_FC_MPIC_IS_MASTER)); OpenPIC = (volatile struct OpenPIC *)&Hydra->OpenPIC; OpenPIC_InitSenses = hydra_openpic_initsenses; OpenPIC_NumInitSenses = sizeof(hydra_openpic_initsenses); return 1; } void __init chrp_pcibios_fixup(void) { struct pci_dev *dev; /* some of IBM chrps have > 1 bus */ if ( !strncmp("IBM", get_property(find_path_device("/"), "name", NULL),3) ) { } /* PCI interrupts are controlled by the OpenPIC */ pci_for_each_dev(dev) { if ( dev->irq ) dev->irq = openpic_to_irq( dev->irq ); /* these need to be absolute addrs for OF and Matrox FB -- Cort */ if ( dev->vendor == PCI_VENDOR_ID_MATROX ) { if ( dev->resource[0].start < isa_mem_base ) dev->resource[0].start += isa_mem_base; if ( dev->resource[1].start < isa_mem_base ) dev->resource[1].start += isa_mem_base; } /* the F50 identifies the amd as a trident */ if ( (dev->vendor == PCI_VENDOR_ID_TRIDENT) && (dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET) ) { dev->vendor = PCI_VENDOR_ID_AMD; pcibios_write_config_word(dev->bus->number, dev->devfn, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); } if ( (dev->bus->number > 0) && ((dev->vendor == PCI_VENDOR_ID_NCR) || (dev->vendor == PCI_VENDOR_ID_AMD))) dev->resource[0].start += (dev->bus->number*0x08000000); } } decl_config_access_method(grackle); decl_config_access_method(indirect); decl_config_access_method(rtas); void __init chrp_setup_pci_ptrs(void) { struct device_node *py; if ( !strncmp("MOT", get_property(find_path_device("/"), "model", NULL),3) ) { pci_dram_offset = 0; isa_mem_base = 0xf7000000; isa_io_base = 0xfe000000; set_config_access_method(grackle); } else { if ( (py = find_compatible_devices( "pci", "IBM,python" )) ) { /* find out how many pythons */ while ( (py = py->next) ) python_busnr++; set_config_access_method(python); /* * We base these values on the machine type but should * try to read them from the python controller itself. * -- Cort */ if ( !strncmp("IBM,7025-F50", get_property(find_path_device("/"), "name", NULL),12) ) { pci_dram_offset = 0x80000000; isa_mem_base = 0xa0000000; isa_io_base = 0x88000000; } else if ( !strncmp("IBM,7043-260", get_property(find_path_device("/"), "name", NULL),12) ) { pci_dram_offset = 0x0; isa_mem_base = 0xc0000000; isa_io_base = 0xf8000000; } } else { if ( !strncmp("IBM,7043-150", get_property(find_path_device("/"), "name", NULL),12) || !strncmp("IBM,7046-155", get_property(find_path_device("/"), "name", NULL),12) || !strncmp("IBM,7046-B50", get_property(find_path_device("/"), "name", NULL),12) ) { pci_dram_offset = 0; isa_mem_base = 0x80000000; isa_io_base = 0xfe000000; pci_config_address = (unsigned int *)0xfec00000; pci_config_data = (unsigned char *)0xfee00000; set_config_access_method(indirect); } else { pci_dram_offset = 0; isa_mem_base = 0xf7000000; isa_io_base = 0xf8000000; set_config_access_method(gg2); } } } ppc_md.pcibios_fixup = chrp_pcibios_fixup; } |