Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 | #include <linux/config.h> #ifndef _ASM_IRQ_H #define _ASM_IRQ_H #include <asm/processor.h> /* for is_prep() */ #ifndef CONFIG_8xx #ifdef CONFIG_APUS #include <asm-m68k/irq.h> #else /* CONFIG_APUS */ /* * this is the # irq's for all ppc arch's (pmac/chrp/prep) * so it is the max of them all - which happens to be powermac * at present (G3 powermacs have 64). */ #define NR_IRQS 64 #endif /* CONFIG_APUS */ #define NUM_8259_INTERRUPTS 16 #define NUM_OPENPIC_INTERRUPTS 20 #define is_8259_irq(n) ((n) < NUM_8259_INTERRUPTS) #define openpic_to_irq(n) ((n)+NUM_8259_INTERRUPTS) #define irq_to_openpic(n) ((n)-NUM_8259_INTERRUPTS) #define IRQ_8259_CASCADE NUM_8259_INTERRUPTS extern void disable_irq(unsigned int); extern void enable_irq(unsigned int); #ifndef CONFIG_APUS /* * This gets called from serial.c, which is now used on * powermacs as well as prep/chrp boxes. * Prep and chrp both have cascaded 8259 PICs. */ static __inline__ int irq_cannonicalize(int irq) { return (((is_prep || is_chrp) && irq == 2) ? 9 : irq); } #endif #else /* CONFIG_8xx */ /* The MPC8xx cores have 16 possible interrupts. There are eight * possible level sensitive interrupts assigned and generated internally * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. * There are eight external interrupts (IRQs) that can be configured * as either level or edge sensitive. * On the MBX implementation, there is also the possibility of an 8259 * through the PCI and PCI-ISA bridges. All 8259 interrupts appear * on the 8xx as IRQ3, but I may eventually add some of the 8259 code * back into this port to handle that controller. */ #define NR_IRQS 16 #define SIU_IRQ0 0 /* Highest priority */ #define SIU_LEVEL0 1 #define SIU_IRQ1 2 #define SIU_LEVEL1 3 #define SIU_IRQ2 4 #define SIU_LEVEL2 5 #define SIU_IRQ3 6 #define SIU_LEVEL3 7 #define SIU_IRQ4 8 #define SIU_LEVEL4 9 #define SIU_IRQ5 10 #define SIU_LEVEL5 11 #define SIU_IRQ6 12 #define SIU_LEVEL6 13 #define SIU_IRQ7 14 #define SIU_LEVEL7 15 /* The internal interrupts we can configure as we see fit. * My personal preference is CPM at level 2, which puts it above the * MBX PCI/ISA/IDE interrupts. */ #define PIT_INTERRUPT SIU_LEVEL0 #define CPM_INTERRUPT SIU_LEVEL2 #define DEC_INTERRUPT SIU_LEVEL7 /* Some internal interrupt registers use an 8-bit mask for the interrupt * level instead of a number. */ #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) #ifdef CONFIG_MBX /* These are defined (and fixed) by the MBX hardware implementation.*/ #define POWER_FAIL_INT SIU_IRQ0 /* Power fail */ #define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */ #define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */ #define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */ #define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */ #define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */ #endif /* CONFIG_MBX */ /* always the same on MBX -- Cort */ static __inline__ int irq_cannonicalize(int irq) { return irq; } #endif /* CONFIG_8xx */ #endif |